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path: root/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c
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Diffstat (limited to 'drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c')
-rw-r--r--drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c146
1 files changed, 143 insertions, 3 deletions
diff --git a/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c
index de126de86f..4dc1fceeca 100644
--- a/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c
+++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c
@@ -1,11 +1,19 @@
/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#ifndef RZG_SOC
+#define RZG_SOC 0
+#endif
+
+#if (RZG_SOC == 1)
+#define BOARDNUM 2
+#else
#define BOARDNUM 22
+#endif /* RZG_SOC == 1 */
#define BOARD_JUDGE_AUTO
#ifdef BOARD_JUDGE_AUTO
@@ -66,6 +74,108 @@ struct _boardcnf {
0x000F,\
0x010F}
+#if (RZG_SOC == 1)
+static const struct _boardcnf boardcnfs[BOARDNUM] = {
+ {
+/* boardcnf[0] HopeRun HiHope RZ/G2M 16Gbit/1rank/2ch board with G2M SoC */
+ .phyvalid = 0x03U,
+ .dbi_en = 0x01U,
+ .cacs_dly = 0x02c0U,
+ .cacs_dly_adj = 0x0U,
+ .dqdm_dly_w = 0x0300U,
+ .dqdm_dly_r = 0x00a0U,
+ .ch = {
+ {
+ { 0x04U, 0xffU },
+ 0x00345201UL,
+ 0x3201U,
+ { 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+ { 0x08U, 0x08U, 0x08U, 0x08U },
+ WDQLVL_PAT,
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 }
+ },
+ {
+ { 0x04U, 0xffU },
+ 0x00302154UL,
+ 0x2310U,
+ { 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+ { 0x08U, 0x08U, 0x08U, 0x08U },
+ WDQLVL_PAT,
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 }
+ }
+ }
+ },
+/* boardcnf[1] HopeRun HiHope RZ/G2M 8Gbit/2rank/2ch board with G2M SoC */
+ {
+ 0x03U,
+ 0x01U,
+ 0x02c0U,
+ 0x0U,
+ 0x0300U,
+ 0x00a0U,
+ {
+ {
+ { 0x02U, 0x02U },
+ 0x00345201UL,
+ 0x3201U,
+ { 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+ { 0x08U, 0x08U, 0x08U, 0x08U },
+ WDQLVL_PAT,
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 }
+ },
+ {
+ { 0x02U, 0x02U },
+ 0x00302154UL,
+ 0x2310,
+ { 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+ { 0x08U, 0x08U, 0x08U, 0x08U },
+ WDQLVL_PAT,
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 }
+ }
+ }
+ }
+};
+#else
static const struct _boardcnf boardcnfs[BOARDNUM] = {
{
/* boardcnf[0] RENESAS SALVATOR-X board with M3-W/SIP */
@@ -1535,6 +1645,7 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
}
}
};
+#endif /* RZG_SOC == 1 */
void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div)
{
@@ -1636,7 +1747,7 @@ static const uint32_t termcode_by_sample[20][3] = {
#define GPIO_INDT5 0xE605500CU
#define GPIO_GPSR6 0xE6060118U
-#if (RCAR_GEN3_ULCB == 0)
+#if (RCAR_GEN3_ULCB == 0) && (RZG_SOC == 0)
static void pfc_write_and_poll(uint32_t a, uint32_t v)
{
mmio_write_32(PFC_PMMR, ~v);
@@ -1652,7 +1763,7 @@ static void pfc_write_and_poll(uint32_t a, uint32_t v)
#define RCAR_GEN3_ULCB 0
#endif
-#if (RCAR_GEN3_ULCB == 0) /* non Starter Kit */
+#if (RCAR_GEN3_ULCB == 0) && (RZG_SOC == 0) /* non Starter Kit */
static uint32_t opencheck_SSI_WS6(void)
{
@@ -1709,9 +1820,37 @@ static uint32_t opencheck_SSI_WS6(void)
#endif
+#if (RZG_SOC == 1)
+#define LPDDR4_2RANK (0x01U << 25U)
+
+static uint32_t rzg2_board_judge(void)
+{
+ uint32_t brd;
+
+ switch (prr_product) {
+ case PRR_PRODUCT_M3:
+ brd = 1U;
+ if ((mmio_read_32(PRR) & PRR_CUT_MASK) != RCAR_M3_CUT_VER11) {
+ if ((mmio_read_32(GPIO_INDT5) & LPDDR4_2RANK) == 0U) {
+ brd = 0U;
+ }
+ }
+ break;
+ default:
+ brd = 99U;
+ }
+
+ return brd;
+}
+#endif /* RZG_SOC == 1 */
+
static uint32_t _board_judge(void)
{
uint32_t brd;
+
+#if (RZG_SOC == 1)
+ brd = rzg2_board_judge();
+#else
#if (RCAR_GEN3_ULCB == 1)
/* Starter Kit */
if (prr_product == PRR_PRODUCT_H3) {
@@ -1798,6 +1937,7 @@ static uint32_t _board_judge(void)
}
}
#endif
+#endif /* RZG_SOC == 1 */
return brd;
}