diff options
Diffstat (limited to 'drivers/renesas/common/ddr/ddr_b/boot_init_dram.c')
-rw-r--r-- | drivers/renesas/common/ddr/ddr_b/boot_init_dram.c | 25 |
1 files changed, 23 insertions, 2 deletions
diff --git a/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c b/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c index aa3bc245b7..3f6a9484de 100644 --- a/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c +++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2021, Renesas Electronics Corporation. + * Copyright (c) 2015-2023, Renesas Electronics Corporation. * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -1180,6 +1180,11 @@ static void regif_pll_wa(void) ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_LP4_BOOT_TOP_PLL_CTRL )); + if (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_LP4_BOOT_LOW_FREQ_SEL)) { + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_LOW_FREQ_SEL), + _cnf_DDR_PHY_ADR_G_REGSET[0x7f & ddr_regdef_adr( + _reg_PHY_LP4_BOOT_LOW_FREQ_SEL)]); + } } reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS), @@ -2856,6 +2861,16 @@ static uint32_t pll3_freq(uint32_t on) timeout = wait_freqchgreq(1); + if ((!((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11))) && (on)) { + if (((1600U * ddr_mbpsdiv) < ddr_mbps) || (prr_product == PRR_PRODUCT_M3)) { + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), 0x01421142U); + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA), 0x00000142U); + } else { + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), 0x03421342U); + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA), 0x00000342U); + } + } + if (timeout) { return 1; } @@ -4147,7 +4162,13 @@ int32_t rcar_dram_init(void) } /* THCTR Bit6: PONM=0 , Bit0: THSST=0 */ - data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE; + data_l = mmio_read_32(THS1_THCTR); + if (data_l & 0x00000040U) { + data_l = data_l & 0xFFFFFFBEU; + } else { + data_l = data_l | BIT(1); + } + mmio_write_32(THS1_THCTR, data_l); /* Judge product and cut */ |