diff options
Diffstat (limited to 'drivers/arm/gic/v3/gic600_multichip_private.h')
-rw-r--r-- | drivers/arm/gic/v3/gic600_multichip_private.h | 44 |
1 files changed, 24 insertions, 20 deletions
diff --git a/drivers/arm/gic/v3/gic600_multichip_private.h b/drivers/arm/gic/v3/gic600_multichip_private.h index fe4134cba9..fd1cb57d2f 100644 --- a/drivers/arm/gic/v3/gic600_multichip_private.h +++ b/drivers/arm/gic/v3/gic600_multichip_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited. All rights reserved. + * Copyright (c) 2019-2023, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,17 +27,11 @@ #define GICD_CHIPSR_RTS_SHIFT 4 #define GICD_DCHIPR_RT_OWNER_SHIFT 4 -/* - * If GIC v4 extension is enabled, then use SPI macros specific to GIC-Clayton. - * Other shifts and mask remains same between GIC-600 and GIC-Clayton. - */ -#if GIC_ENABLE_V4_EXTN -#define GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT 9 -#define GICD_CHIPRx_SPI_BLOCKS_SHIFT 3 -#else -#define GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT 10 -#define GICD_CHIPRx_SPI_BLOCKS_SHIFT 5 -#endif +/* Other shifts and masks remain the same between GIC-600 and GIC-700. */ +#define GIC_700_SPI_BLOCK_MIN_SHIFT 9 +#define GIC_700_SPI_BLOCKS_SHIFT 3 +#define GIC_600_SPI_BLOCK_MIN_SHIFT 10 +#define GIC_600_SPI_BLOCKS_SHIFT 5 #define GICD_CHIPSR_RTS_STATE_DISCONNECTED U(0) #define GICD_CHIPSR_RTS_STATE_UPDATING U(1) @@ -45,30 +39,40 @@ /* SPI interrupt id minimum and maximum range */ #define GIC600_SPI_ID_MIN 32 -#define GIC600_SPI_ID_MAX 960 +#define GIC600_SPI_ID_MAX 991 + +#define GIC700_SPI_ID_MIN 32 +#define GIC700_SPI_ID_MAX 991 +#define GIC700_ESPI_ID_MIN 4096 +#define GIC700_ESPI_ID_MAX 5119 /* Number of retries for PUP update */ #define GICD_PUP_UPDATE_RETRIES 10000 -#define SPI_MIN_INDEX 0 -#define SPI_MAX_INDEX 1 - #define SPI_BLOCK_MIN_VALUE(spi_id_min) \ (((spi_id_min) - GIC600_SPI_ID_MIN) / \ GIC600_SPI_ID_MIN) #define SPI_BLOCKS_VALUE(spi_id_min, spi_id_max) \ (((spi_id_max) - (spi_id_min) + 1) / \ GIC600_SPI_ID_MIN) -#define GICD_CHIPR_VALUE(chip_addr, spi_block_min, spi_blocks) \ +#define ESPI_BLOCK_MIN_VALUE(spi_id_min) \ + (((spi_id_min) - GIC700_ESPI_ID_MIN + 1) / \ + GIC700_SPI_ID_MIN) +#define GICD_CHIPR_VALUE_GIC_700(chip_addr, spi_block_min, spi_blocks) \ + (((chip_addr) << GICD_CHIPRx_ADDR_SHIFT) | \ + ((spi_block_min) << GIC_700_SPI_BLOCK_MIN_SHIFT) | \ + ((spi_blocks) << GIC_700_SPI_BLOCKS_SHIFT)) +#define GICD_CHIPR_VALUE_GIC_600(chip_addr, spi_block_min, spi_blocks) \ (((chip_addr) << GICD_CHIPRx_ADDR_SHIFT) | \ - ((spi_block_min) << GICD_CHIPRx_SPI_BLOCK_MIN_SHIFT) | \ - ((spi_blocks) << GICD_CHIPRx_SPI_BLOCKS_SHIFT)) + ((spi_block_min) << GIC_600_SPI_BLOCK_MIN_SHIFT) | \ + ((spi_blocks) << GIC_600_SPI_BLOCKS_SHIFT)) /* * Multichip data assertion macros */ /* Set bits from 0 to ((spi_id_max + 1) / 32) */ -#define SPI_BLOCKS_TILL_MAX(spi_id_max) ((1 << (((spi_id_max) + 1) >> 5)) - 1) +#define SPI_BLOCKS_TILL_MAX(spi_id_max) \ + ((1ULL << (((spi_id_max) + 1) >> 5)) - 1) /* Set bits from 0 to (spi_id_min / 32) */ #define SPI_BLOCKS_TILL_MIN(spi_id_min) ((1 << ((spi_id_min) >> 5)) - 1) /* Set bits from (spi_id_min / 32) to ((spi_id_max + 1) / 32) */ |