diff options
19 files changed, 3046 insertions, 3331 deletions
diff --git a/docs/components/sdei.rst b/docs/components/sdei.rst index 6d0e1563d6..2a777b385b 100644 --- a/docs/components/sdei.rst +++ b/docs/components/sdei.rst @@ -26,7 +26,7 @@ The following figure depicts a general sequence involving SDEI client executing at EL2 and an event dispatch resulting from the triggering of a bound interrupt. A commentary is provided below: -.. image:: ../resources/diagrams/plantuml/sdei_general.svg +.. uml:: ../resources/diagrams/plantuml/sdei_general.puml As part of initialisation, the SDEI client binds a Non-secure interrupt [1], and the SDEI dispatcher returns a platform dynamic event number [2]. The client then @@ -234,7 +234,7 @@ on success, or ``-1`` on failure. The following figure depicts a scenario involving explicit dispatch of SDEI event. A commentary is provided below: -.. image:: ../resources/diagrams/plantuml/sdei_explicit_dispatch.svg +.. uml:: ../resources/diagrams/plantuml/sdei_explicit_dispatch.puml As part of initialisation, the SDEI client registers a handler for a platform event [1], enables the event [3], and unmasks the current PE [5]. Note that, diff --git a/docs/conf.py b/docs/conf.py index 64f12431bb..b267de0e86 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -23,7 +23,7 @@ release = version # We don't need these to be distinct # Add any Sphinx extension module names here, as strings. They can be # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom # ones. -extensions = ['sphinx.ext.autosectionlabel'] +extensions = ['sphinx.ext.autosectionlabel', 'sphinxcontrib.plantuml'] # Add any paths that contain templates here, relative to this directory. templates_path = ['_templates'] @@ -82,4 +82,8 @@ html_theme_options = { # -- Options for autosectionlabel -------------------------------------------- # Only generate automatic section labels for document titles -autosectionlabel_maxdepth = 1
\ No newline at end of file +autosectionlabel_maxdepth = 1 + +# -- Options for plantuml ---------------------------------------------------- + +plantuml_output_format = 'svg_img' diff --git a/docs/requirements.txt b/docs/requirements.txt index 8f95774b6b..358ed0e3cc 100644 --- a/docs/requirements.txt +++ b/docs/requirements.txt @@ -1,2 +1,3 @@ sphinx>=2.0.0 -sphinx-rtd-theme>=0.4.3
\ No newline at end of file +sphinx-rtd-theme>=0.4.3 +sphinxcontrib-plantuml>=0.15 diff --git a/docs/resources/diagrams/plantuml/plantuml_to_svg.sh b/docs/resources/diagrams/plantuml/plantuml_to_svg.sh deleted file mode 100644 index 0bf8588bba..0000000000 --- a/docs/resources/diagrams/plantuml/plantuml_to_svg.sh +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/bash - -# Convert all PlantUML files in this directory to SVG files. The plantuml_jar -# environment variable must be set to the path to PlantUML JAR file. - -if [ -z "$plantuml_jar" ]; then - echo "Usage: plantuml_jar=/path/to/plantuml.jar $0 *.puml" >&2 - exit 1 -fi - -java -jar "$plantuml_jar" -nometadata -tsvg "$@" - -# vim:set noet sts=8 tw=80: diff --git a/docs/resources/diagrams/plantuml/sdei_explicit_dispatch.svg b/docs/resources/diagrams/plantuml/sdei_explicit_dispatch.svg deleted file mode 100644 index e12cae2faa..0000000000 --- a/docs/resources/diagrams/plantuml/sdei_explicit_dispatch.svg +++ /dev/null @@ -1 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?><svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" contentScriptType="application/ecmascript" contentStyleType="text/css" height="783px" preserveAspectRatio="none" style="width:745px;height:783px;" version="1.1" viewBox="0 0 745 783" width="745px" zoomAndPan="magnify"><defs><filter height="300%" id="f18zq03ani7xpz" width="300%" x="-1" y="-1"><feGaussianBlur result="blurOut" stdDeviation="2.0"/><feColorMatrix in="blurOut" result="blurOut2" type="matrix" values="0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .4 0"/><feOffset dx="4.0" dy="4.0" in="blurOut2" result="blurOut3"/><feBlend in="SourceGraphic" in2="blurOut3" mode="normal"/></filter></defs><g><rect fill="#FFFFFF" filter="url(#f18zq03ani7xpz)" height="174.7969" style="stroke: #FFFFFF; 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\ No newline at end of file diff --git a/drivers/console/aarch32/skeleton_console.S b/drivers/console/aarch32/skeleton_console.S index da4cecd33f..45ad139275 100644 --- a/drivers/console/aarch32/skeleton_console.S +++ b/drivers/console/aarch32/skeleton_console.S @@ -1,108 +1,176 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <asm_macros.S> +#include <console_macros.S> /* - * This file contains a skeleton console implementation that can - * be used as basis for a real console implementation by platforms - * that do not contain PL011 hardware. + * This file contains a skeleton console driver that can be used as a + * basis for a real console driver. Console drivers in Trusted Firmware + * can be instantiated multiple times. Each instance is described by a + * separate console_t structure which must be registered with the common + * console framework via console_register(). Console drivers should + * define a console_xxx_register() function that initializes a new + * console_t structure passed in from the caller and registers it after + * initializing the console hardware. Drivers may define their own + * structures extending console_t to store private driver information. + * Console drivers *MUST* ensure that the console callbacks they + * implement only change registers allowed in the clobber lists defined + * in this file. (Note that in addition to the explicit clobber lists, + * any function may always clobber the intra-procedure-call register + * r12, but may never depend on it retaining its value across any + * function call.) */ - .globl console_core_init - .globl console_core_putc - .globl console_core_getc - .globl console_core_flush + .globl console_xxx_register + .globl console_xxx_putc + .globl console_xxx_getc + .globl console_xxx_flush /* ----------------------------------------------- - * int console_core_init(uintptr_t base_addr, - * unsigned int uart_clk, unsigned int baud_rate) - * Function to initialize the console without a - * C Runtime to print debug information. This - * function will be accessed by console_init and - * crash reporting. - * In: r0 - console base address - * r1 - Uart clock in Hz - * r2 - Baud rate - * Out: return 1 on success else 0 on error - * Clobber list : r1, r2 + * int console_xxx_register(console_xxx_t *console, + * ...additional parameters as desired...) + * Function to initialize and register the console. + * The caller needs to pass an empty console_xxx_t + * structure in which *MUST* be allocated in + * persistent memory (e.g. a global or static local + * variable, *NOT* on the stack). + * In : r0 - pointer to empty console_t structure + * r1 through r7: additional parameters as desired + * Out: r0 - 1 on success, 0 on error + * Clobber list : r0 - r7 * ----------------------------------------------- */ -func console_core_init - /* Check the input base address */ - cmp r0, #0 - beq core_init_fail - /* Check baud rate and uart clock for sanity */ - cmp r1, #0 - beq core_init_fail - cmp r2, #0 - beq core_init_fail - /* Insert implementation here */ - mov r0, #1 - bx lr -core_init_fail: +func console_xxx_register + /* + * Store parameters (e.g. hardware base address) in driver-specific + * console_xxx_t structure field if they will need to be retrieved + * by later console callback (e.g. putc). + * Example: + */ + str r1, [r0, #CONSOLE_T_XXX_BASE] + str r2, [r0, #CONSOLE_T_XXX_SOME_OTHER_VALUE] + + /* + * Initialize console hardware, using r1 - r7 parameters as needed. + * Keep console_t pointer in r0 for later. + */ + + /* + * Macro to finish up registration and return (needs valid r0 + lr). + * If any of the argument is unspecified, then the corresponding + * entry in console_t is set to 0. + */ + finish_console_register xxx putc=1, getc=1, flush=1 + + /* Jump here if hardware init fails or parameters are invalid. */ +register_fail: mov r0, #0 bx lr -endfunc console_core_init +endfunc console_xxx_register /* -------------------------------------------------------- - * int console_core_putc(int c, uintptr_t base_addr) + * int console_xxx_putc(int c, console_xxx_t *console) * Function to output a character over the console. It * returns the character printed on success or -1 on error. * In : r0 - character to be printed - * r1 - console base address - * Out : return -1 on error else return character. - * Clobber list : r2 + * r1 - pointer to console_t struct + * Out: r0 - printed character on success, < 0 on error. + * Clobber list : r0, r1, r2 * -------------------------------------------------------- */ -func console_core_putc - /* Check the input parameter */ - cmp r1, #0 - beq putc_error - /* Insert implementation here */ +func console_xxx_putc + /* + * Retrieve values we need (e.g. hardware base address) from + * console_xxx_t structure pointed to by r1. + * Example: + */ + ldr r1, [r1, #CONSOLE_T_XXX_BASE] + + /* + * Write r0 to hardware. + */ + bx lr + + /* Jump here if output fails for any reason. */ putc_error: mov r0, #-1 bx lr -endfunc console_core_putc +endfunc console_xxx_putc /* --------------------------------------------- - * int console_core_getc(uintptr_t base_addr) + * int console_xxx_getc(console_xxx_t *console) * Function to get a character from the console. - * It returns the character grabbed on success - * or -1 on error. - * In : r0 - console base address + * Even though console_getc() is blocking, this + * callback has to be non-blocking and always + * return immediately to allow polling multiple + * drivers concurrently. + * Returns the character grabbed on success, + * ERROR_NO_PENDING_CHAR if no character was + * available at this time, or any value + * between -2 and -127 if there was an error. + * In : r0 - pointer to console_t struct + * Out: r0 - character on success, + * ERROR_NO_PENDING_CHAR if no char, + * < -1 on error * Clobber list : r0, r1 * --------------------------------------------- */ -func console_core_getc - cmp r0, #0 - beq getc_error - /* Insert implementation here */ +func console_xxx_getc + /* + * Retrieve values we need (e.g. hardware base address) from + * console_xxx_t structure pointed to by r0. + * Example: + */ + ldr r1, [r0, #CONSOLE_T_XXX_BASE] + + /* + * Try to read character into r0 from hardware. + */ + bx lr + + /* Jump here if there is no character available at this time. */ +getc_no_char: + mov r0, #ERROR_NO_PENDING_CHAR + bx lr + + /* Jump here if there was any hardware error. */ getc_error: - mov r0, #-1 + mov r0, #-2 /* may pick error codes between -2 and -127 */ bx lr -endfunc console_core_getc +endfunc console_xxx_getc /* --------------------------------------------- - * int console_core_flush(uintptr_t base_addr) + * int console_xxx_flush(console_xxx_t *console) * Function to force a write of all buffered * data that hasn't been output. - * In : r0 - console base address - * Out : return -1 on error else return 0. - * Clobber list : r0, r1 + * In : r0 - pointer to console_xxx_t struct + * Out: r0 - 0 on success, < 0 on error + * Clobber list : r0, r1, r2, r3, r4, r5 * --------------------------------------------- */ -func console_core_flush - cmp r0, #0 - beq flush_error - /* Insert implementation here */ +func console_xxx_flush + /* + * Retrieve values we need (e.g. hardware base address) from + * console_xxx_t structure pointed to by r0. + * Example: + */ + ldr r1, [r0, #CONSOLE_T_XXX_BASE] + + /* + * Flush all remaining output from hardware FIFOs. Do not return until + * all data has been flushed or there was an unrecoverable error. + */ + mov r0, #0 bx lr + + /* Jump here if an unrecoverable error has been encountered. */ flush_error: mov r0, #-1 bx lr -endfunc console_core_flush +endfunc console_xxx_flush diff --git a/drivers/console/aarch64/skeleton_console.S b/drivers/console/aarch64/skeleton_console.S index c695ddec46..957ed83a96 100644 --- a/drivers/console/aarch64/skeleton_console.S +++ b/drivers/console/aarch64/skeleton_console.S @@ -7,7 +7,7 @@ #include <console_macros.S> /* - * This file contains a skeleton console driver that can be used as + * This file contains a skeleton console driver that can be used as a * basis for a real console driver. Console drivers in Trusted Firmware * can be instantiated multiple times. Each instance is described by a * separate console_t structure which must be registered with the common @@ -16,7 +16,7 @@ * console_t structure passed in from the caller and registers it after * initializing the console hardware. Drivers may define their own * structures extending console_t to store private driver information. - * Console drivers *MUST* take care that the console callbacks they + * Console drivers *MUST* ensure that the console callbacks they * implement only change registers allowed in the clobber lists defined * in this file. (Note that in addition to the explicit clobber lists, * any function may always clobber the intra-procedure-call registers diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h new file mode 100644 index 0000000000..397bde04e0 --- /dev/null +++ b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h @@ -0,0 +1,291 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef BOOT_INIT_DRAM_REGDEF_H_ +#define BOOT_INIT_DRAM_REGDEF_H_ + +/* DBSC registers */ +#define DBSC_DBSYSCONF0 0xE6790000U +#define DBSC_DBSYSCONF1 0xE6790004U +#define DBSC_DBPHYCONF0 0xE6790010U +#define DBSC_DBKIND 0xE6790020U +#define DBSC_DBMEMCONF00 0xE6790030U +#define DBSC_DBMEMCONF01 0xE6790034U +#define DBSC_DBMEMCONF02 0xE6790038U +#define DBSC_DBMEMCONF03 0xE679003CU +#define DBSC_DBMEMCONF10 0xE6790040U +#define DBSC_DBMEMCONF11 0xE6790044U +#define DBSC_DBMEMCONF12 0xE6790048U +#define DBSC_DBMEMCONF13 0xE679004CU +#define DBSC_DBMEMCONF20 0xE6790050U +#define DBSC_DBMEMCONF21 0xE6790054U +#define DBSC_DBMEMCONF22 0xE6790058U +#define DBSC_DBMEMCONF23 0xE679005CU +#define DBSC_DBMEMCONF30 0xE6790060U +#define DBSC_DBMEMCONF31 0xE6790064U +#define DBSC_DBMEMCONF32 0xE6790068U +#define DBSC_DBMEMCONF33 0xE679006CU +#define DBSC_DBSYSCNT0 0xE6790100U +#define DBSC_DBSVCR1 0xE6790104U +#define DBSC_DBSTATE0 0xE6790108U +#define DBSC_DBSTATE1 0xE679010CU +#define DBSC_DBINTEN 0xE6790180U +#define DBSC_DBINTSTAT0 0xE6790184U +#define DBSC_DBACEN 0xE6790200U +#define DBSC_DBRFEN 0xE6790204U +#define DBSC_DBCMD 0xE6790208U +#define DBSC_DBWAIT 0xE6790210U +#define DBSC_DBSYSCTRL0 0xE6790280U +#define DBSC_DBTR0 0xE6790300U +#define DBSC_DBTR1 0xE6790304U +#define DBSC_DBTR2 0xE6790308U +#define DBSC_DBTR3 0xE679030CU +#define DBSC_DBTR4 0xE6790310U +#define DBSC_DBTR5 0xE6790314U +#define DBSC_DBTR6 0xE6790318U +#define DBSC_DBTR7 0xE679031CU +#define DBSC_DBTR8 0xE6790320U +#define DBSC_DBTR9 0xE6790324U +#define DBSC_DBTR10 0xE6790328U +#define DBSC_DBTR11 0xE679032CU +#define DBSC_DBTR12 0xE6790330U +#define DBSC_DBTR13 0xE6790334U +#define DBSC_DBTR14 0xE6790338U +#define DBSC_DBTR15 0xE679033CU +#define DBSC_DBTR16 0xE6790340U +#define DBSC_DBTR17 0xE6790344U +#define DBSC_DBTR18 0xE6790348U +#define DBSC_DBTR19 0xE679034CU +#define DBSC_DBTR20 0xE6790350U +#define DBSC_DBTR21 0xE6790354U +#define DBSC_DBTR22 0xE6790358U +#define DBSC_DBTR23 0xE679035CU +#define DBSC_DBTR24 0xE6790360U +#define DBSC_DBTR25 0xE6790364U +#define DBSC_DBBL 0xE6790400U +#define DBSC_DBRFCNF1 0xE6790414U +#define DBSC_DBRFCNF2 0xE6790418U +#define DBSC_DBTSPCNF 0xE6790420U +#define DBSC_DBCALCNF 0xE6790424U +#define DBSC_DBRNK2 0xE6790438U +#define DBSC_DBRNK3 0xE679043CU +#define DBSC_DBRNK4 0xE6790440U +#define DBSC_DBRNK5 0xE6790444U +#define DBSC_DBPDNCNF 0xE6790450U +#define DBSC_DBODT0 0xE6790460U +#define DBSC_DBODT1 0xE6790464U +#define DBSC_DBODT2 0xE6790468U +#define DBSC_DBODT3 0xE679046CU +#define DBSC_DBODT4 0xE6790470U +#define DBSC_DBODT5 0xE6790474U +#define DBSC_DBODT6 0xE6790478U +#define DBSC_DBODT7 0xE679047CU +#define DBSC_DBADJ0 0xE6790500U +#define DBSC_DBDBICNT 0xE6790518U +#define DBSC_DBDFIPMSTRCNF 0xE6790520U +#define DBSC_DBDFIPMSTRSTAT 0xE6790524U +#define DBSC_DBDFILPCNF 0xE6790528U +#define DBSC_DBDFICUPDCNF 0xE679052CU +#define DBSC_DBDFISTAT0 0xE6790600U +#define DBSC_DBDFICNT0 0xE6790604U +#define DBSC_DBPDCNT00 0xE6790610U +#define DBSC_DBPDCNT01 0xE6790614U +#define DBSC_DBPDCNT02 0xE6790618U +#define DBSC_DBPDCNT03 0xE679061CU +#define DBSC_DBPDLK0 0xE6790620U +#define DBSC_DBPDRGA0 0xE6790624U +#define DBSC_DBPDRGD0 0xE6790628U +#define DBSC_DBPDSTAT00 0xE6790630U +#define DBSC_DBDFISTAT1 0xE6790640U +#define DBSC_DBDFICNT1 0xE6790644U +#define DBSC_DBPDCNT10 0xE6790650U +#define DBSC_DBPDCNT11 0xE6790654U +#define DBSC_DBPDCNT12 0xE6790658U +#define DBSC_DBPDCNT13 0xE679065CU +#define DBSC_DBPDLK1 0xE6790660U +#define DBSC_DBPDRGA1 0xE6790664U +#define DBSC_DBPDRGD1 0xE6790668U +#define DBSC_DBPDSTAT10 0xE6790670U +#define DBSC_DBDFISTAT2 0xE6790680U +#define DBSC_DBDFICNT2 0xE6790684U +#define DBSC_DBPDCNT20 0xE6790690U +#define DBSC_DBPDCNT21 0xE6790694U +#define DBSC_DBPDCNT22 0xE6790698U +#define DBSC_DBPDCNT23 0xE679069CU +#define DBSC_DBPDLK2 0xE67906A0U +#define DBSC_DBPDRGA2 0xE67906A4U +#define DBSC_DBPDRGD2 0xE67906A8U +#define DBSC_DBPDSTAT20 0xE67906B0U +#define DBSC_DBDFISTAT3 0xE67906C0U +#define DBSC_DBDFICNT3 0xE67906C4U +#define DBSC_DBPDCNT30 0xE67906D0U +#define DBSC_DBPDCNT31 0xE67906D4U +#define DBSC_DBPDCNT32 0xE67906D8U +#define DBSC_DBPDCNT33 0xE67906DCU +#define DBSC_DBPDLK3 0xE67906E0U +#define DBSC_DBPDRGA3 0xE67906E4U +#define DBSC_DBPDRGD3 0xE67906E8U +#define DBSC_DBPDSTAT30 0xE67906F0U +#define DBSC_DBBUS0CNF0 0xE6790800U +#define DBSC_DBBUS0CNF1 0xE6790804U +#define DBSC_DBCAM0CNF1 0xE6790904U +#define DBSC_DBCAM0CNF2 0xE6790908U +#define DBSC_DBCAM0CNF3 0xE679090CU +#define DBSC_DBCAM0CTRL0 0xE6790940U +#define DBSC_DBCAM0STAT0 0xE6790980U +#define DBSC_DBCAM1STAT0 0xE6790990U +#define DBSC_DBBCAMSWAP 0xE67909F0U +#define DBSC_DBBCAMDIS 0xE67909FCU +#define DBSC_DBSCHCNT0 0xE6791000U +#define DBSC_DBSCHCNT1 0xE6791004U +#define DBSC_DBSCHSZ0 0xE6791010U +#define DBSC_DBSCHRW0 0xE6791020U +#define DBSC_DBSCHRW1 0xE6791024U +#define DBSC_DBSCHQOS00 0xE6791030U +#define DBSC_DBSCHQOS01 0xE6791034U +#define DBSC_DBSCHQOS02 0xE6791038U +#define DBSC_DBSCHQOS03 0xE679103CU +#define DBSC_DBSCHQOS10 0xE6791040U +#define DBSC_DBSCHQOS11 0xE6791044U +#define DBSC_DBSCHQOS12 0xE6791048U +#define DBSC_DBSCHQOS13 0xE679104CU +#define DBSC_DBSCHQOS20 0xE6791050U +#define DBSC_DBSCHQOS21 0xE6791054U +#define DBSC_DBSCHQOS22 0xE6791058U +#define DBSC_DBSCHQOS23 0xE679105CU +#define DBSC_DBSCHQOS30 0xE6791060U +#define DBSC_DBSCHQOS31 0xE6791064U +#define DBSC_DBSCHQOS32 0xE6791068U +#define DBSC_DBSCHQOS33 0xE679106CU +#define DBSC_DBSCHQOS40 0xE6791070U +#define DBSC_DBSCHQOS41 0xE6791074U +#define DBSC_DBSCHQOS42 0xE6791078U +#define DBSC_DBSCHQOS43 0xE679107CU +#define DBSC_DBSCHQOS50 0xE6791080U +#define DBSC_DBSCHQOS51 0xE6791084U +#define DBSC_DBSCHQOS52 0xE6791088U +#define DBSC_DBSCHQOS53 0xE679108CU +#define DBSC_DBSCHQOS60 0xE6791090U +#define DBSC_DBSCHQOS61 0xE6791094U +#define DBSC_DBSCHQOS62 0xE6791098U +#define DBSC_DBSCHQOS63 0xE679109CU +#define DBSC_DBSCHQOS70 0xE67910A0U +#define DBSC_DBSCHQOS71 0xE67910A4U +#define DBSC_DBSCHQOS72 0xE67910A8U +#define DBSC_DBSCHQOS73 0xE67910ACU +#define DBSC_DBSCHQOS80 0xE67910B0U +#define DBSC_DBSCHQOS81 0xE67910B4U +#define DBSC_DBSCHQOS82 0xE67910B8U +#define DBSC_DBSCHQOS83 0xE67910BCU +#define DBSC_DBSCHQOS90 0xE67910C0U +#define DBSC_DBSCHQOS91 0xE67910C4U +#define DBSC_DBSCHQOS92 0xE67910C8U +#define DBSC_DBSCHQOS93 0xE67910CCU +#define DBSC_DBSCHQOS100 0xE67910D0U +#define DBSC_DBSCHQOS101 0xE67910D4U +#define DBSC_DBSCHQOS102 0xE67910D8U +#define DBSC_DBSCHQOS103 0xE67910DCU +#define DBSC_DBSCHQOS110 0xE67910E0U +#define DBSC_DBSCHQOS111 0xE67910E4U +#define DBSC_DBSCHQOS112 0xE67910E8U +#define DBSC_DBSCHQOS113 0xE67910ECU +#define DBSC_DBSCHQOS120 0xE67910F0U +#define DBSC_DBSCHQOS121 0xE67910F4U +#define DBSC_DBSCHQOS122 0xE67910F8U +#define DBSC_DBSCHQOS123 0xE67910FCU +#define DBSC_DBSCHQOS130 0xE6791100U +#define DBSC_DBSCHQOS131 0xE6791104U +#define DBSC_DBSCHQOS132 0xE6791108U +#define DBSC_DBSCHQOS133 0xE679110CU +#define DBSC_DBSCHQOS140 0xE6791110U +#define DBSC_DBSCHQOS141 0xE6791114U +#define DBSC_DBSCHQOS142 0xE6791118U +#define DBSC_DBSCHQOS143 0xE679111CU +#define DBSC_DBSCHQOS150 0xE6791120U +#define DBSC_DBSCHQOS151 0xE6791124U +#define DBSC_DBSCHQOS152 0xE6791128U +#define DBSC_DBSCHQOS153 0xE679112CU +#define DBSC_SCFCTST0 0xE6791700U +#define DBSC_SCFCTST1 0xE6791708U +#define DBSC_SCFCTST2 0xE679170CU +#define DBSC_DBMRRDR0 0xE6791800U +#define DBSC_DBMRRDR1 0xE6791804U +#define DBSC_DBMRRDR2 0xE6791808U +#define DBSC_DBMRRDR3 0xE679180CU +#define DBSC_DBMRRDR4 0xE6791810U +#define DBSC_DBMRRDR5 0xE6791814U +#define DBSC_DBMRRDR6 0xE6791818U +#define DBSC_DBMRRDR7 0xE679181CU +#define DBSC_DBDTMP0 0xE6791820U +#define DBSC_DBDTMP1 0xE6791824U +#define DBSC_DBDTMP2 0xE6791828U +#define DBSC_DBDTMP3 0xE679182CU +#define DBSC_DBDTMP4 0xE6791830U +#define DBSC_DBDTMP5 0xE6791834U +#define DBSC_DBDTMP6 0xE6791838U +#define DBSC_DBDTMP7 0xE679183CU +#define DBSC_DBDQSOSC00 0xE6791840U +#define DBSC_DBDQSOSC01 0xE6791844U +#define DBSC_DBDQSOSC10 0xE6791848U +#define DBSC_DBDQSOSC11 0xE679184CU +#define DBSC_DBDQSOSC20 0xE6791850U +#define DBSC_DBDQSOSC21 0xE6791854U +#define DBSC_DBDQSOSC30 0xE6791858U +#define DBSC_DBDQSOSC31 0xE679185CU +#define DBSC_DBDQSOSC40 0xE6791860U +#define DBSC_DBDQSOSC41 0xE6791864U +#define DBSC_DBDQSOSC50 0xE6791868U +#define DBSC_DBDQSOSC51 0xE679186CU +#define DBSC_DBDQSOSC60 0xE6791870U +#define DBSC_DBDQSOSC61 0xE6791874U +#define DBSC_DBDQSOSC70 0xE6791878U +#define DBSC_DBDQSOSC71 0xE679187CU +#define DBSC_DBOSCTHH00 0xE6791880U +#define DBSC_DBOSCTHH01 0xE6791884U +#define DBSC_DBOSCTHH10 0xE6791888U +#define DBSC_DBOSCTHH11 0xE679188CU +#define DBSC_DBOSCTHH20 0xE6791890U +#define DBSC_DBOSCTHH21 0xE6791894U +#define DBSC_DBOSCTHH30 0xE6791898U +#define DBSC_DBOSCTHH31 0xE679189CU +#define DBSC_DBOSCTHH40 0xE67918A0U +#define DBSC_DBOSCTHH41 0xE67918A4U +#define DBSC_DBOSCTHH50 0xE67918A8U +#define DBSC_DBOSCTHH51 0xE67918ACU +#define DBSC_DBOSCTHH60 0xE67918B0U +#define DBSC_DBOSCTHH61 0xE67918B4U +#define DBSC_DBOSCTHH70 0xE67918B8U +#define DBSC_DBOSCTHH71 0xE67918BCU +#define DBSC_DBOSCTHL00 0xE67918C0U +#define DBSC_DBOSCTHL01 0xE67918C4U +#define DBSC_DBOSCTHL10 0xE67918C8U +#define DBSC_DBOSCTHL11 0xE67918CCU +#define DBSC_DBOSCTHL20 0xE67918D0U +#define DBSC_DBOSCTHL21 0xE67918D4U +#define DBSC_DBOSCTHL30 0xE67918D8U +#define DBSC_DBOSCTHL31 0xE67918DCU +#define DBSC_DBOSCTHL40 0xE67918E0U +#define DBSC_DBOSCTHL41 0xE67918E4U +#define DBSC_DBOSCTHL50 0xE67918E8U +#define DBSC_DBOSCTHL51 0xE67918ECU +#define DBSC_DBOSCTHL60 0xE67918F0U +#define DBSC_DBOSCTHL61 0xE67918F4U +#define DBSC_DBOSCTHL70 0xE67918F8U +#define DBSC_DBOSCTHL71 0xE67918FCU +#define DBSC_DBMEMSWAPCONF0 0xE6792000U + +/* CPG registers */ +#define CPG_SRCR4 0xE61500BCU +#define CPG_PLLECR 0xE61500D0U +#define CPG_CPGWPR 0xE6150900U +#define CPG_CPGWPCR 0xE6150904U +#define CPG_SRSTCLR4 0xE6150950U + +/* MODE Monitor registers */ +#define RST_MODEMR 0xE6160060U + +#endif /* BOOT_INIT_DRAM_REGDEF_H_*/ diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_d3.h b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_d3.h deleted file mode 100644 index e157ab1ce6..0000000000 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_d3.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Copyright (c) 2015-2017, Renesas Electronics Corporation - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* - * Revision history - * - * rev.0.01 2017/05/22 New - */ - -#ifndef BOOT_INIT_DRAM_REGDEF_D3_H_ -#define BOOT_INIT_DRAM_REGDEF_D3_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define BIT0 0x00000001U -#define BIT30 0x40000000U - -/* DBSC registers */ - -#define DBSC_D3_DBSYSCONF1 0xE6790004U -#define DBSC_D3_DBPHYCONF0 0xE6790010U -#define DBSC_D3_DBKIND 0xE6790020U -#define DBSC_D3_DBMEMCONF00 0xE6790030U -#define DBSC_D3_DBMEMCONF01 0xE6790034U -#define DBSC_D3_DBMEMCONF02 0xE6790038U -#define DBSC_D3_DBMEMCONF03 0xE679003CU -#define DBSC_D3_DBMEMCONF10 0xE6790040U -#define DBSC_D3_DBMEMCONF11 0xE6790044U -#define DBSC_D3_DBMEMCONF12 0xE6790048U -#define DBSC_D3_DBMEMCONF13 0xE679004CU -#define DBSC_D3_DBMEMCONF20 0xE6790050U -#define DBSC_D3_DBMEMCONF21 0xE6790054U -#define DBSC_D3_DBMEMCONF22 0xE6790058U -#define DBSC_D3_DBMEMCONF23 0xE679005CU -#define DBSC_D3_DBMEMCONF30 0xE6790060U -#define DBSC_D3_DBMEMCONF31 0xE6790064U -#define DBSC_D3_DBMEMCONF32 0xE6790068U -#define DBSC_D3_DBMEMCONF33 0xE679006CU -#define DBSC_D3_DBSYSCNT0 0xE6790100U -#define DBSC_D3_DBSVCR1 0xE6790104U -#define DBSC_D3_DBSTATE0 0xE6790108U -#define DBSC_D3_DBSTATE1 0xE679010CU -#define DBSC_D3_DBINTEN 0xE6790180U -#define DBSC_D3_DBINTSTAT0 0xE6790184U -#define DBSC_D3_DBACEN 0xE6790200U -#define DBSC_D3_DBRFEN 0xE6790204U -#define DBSC_D3_DBCMD 0xE6790208U -#define DBSC_D3_DBWAIT 0xE6790210U -#define DBSC_D3_DBSYSCTRL0 0xE6790280U -#define DBSC_D3_DBTR0 0xE6790300U -#define DBSC_D3_DBTR1 0xE6790304U -#define DBSC_D3_DBTR2 0xE6790308U -#define DBSC_D3_DBTR3 0xE679030CU -#define DBSC_D3_DBTR4 0xE6790310U -#define DBSC_D3_DBTR5 0xE6790314U -#define DBSC_D3_DBTR6 0xE6790318U -#define DBSC_D3_DBTR7 0xE679031CU -#define DBSC_D3_DBTR8 0xE6790320U -#define DBSC_D3_DBTR9 0xE6790324U -#define DBSC_D3_DBTR10 0xE6790328U -#define DBSC_D3_DBTR11 0xE679032CU -#define DBSC_D3_DBTR12 0xE6790330U -#define DBSC_D3_DBTR13 0xE6790334U -#define DBSC_D3_DBTR14 0xE6790338U -#define DBSC_D3_DBTR15 0xE679033CU -#define DBSC_D3_DBTR16 0xE6790340U -#define DBSC_D3_DBTR17 0xE6790344U -#define DBSC_D3_DBTR18 0xE6790348U -#define DBSC_D3_DBTR19 0xE679034CU -#define DBSC_D3_DBTR20 0xE6790350U -#define DBSC_D3_DBTR21 0xE6790354U -#define DBSC_D3_DBTR22 0xE6790358U -#define DBSC_D3_DBTR24 0xE6790360U -#define DBSC_D3_DBTR25 0xE6790364U -#define DBSC_D3_DBBL 0xE6790400U -#define DBSC_D3_DBRFCNF1 0xE6790414U -#define DBSC_D3_DBRFCNF2 0xE6790418U -#define DBSC_D3_DBCALCNF 0xE6790424U -#define DBSC_D3_DBRNK2 0xE6790438U -#define DBSC_D3_DBRNK3 0xE679043CU -#define DBSC_D3_DBRNK4 0xE6790440U -#define DBSC_D3_DBRNK5 0xE6790444U -#define DBSC_D3_DBPDNCNF 0xE6790450U -#define DBSC_D3_DBODT0 0xE6790460U -#define DBSC_D3_DBODT1 0xE6790464U -#define DBSC_D3_DBODT2 0xE6790468U -#define DBSC_D3_DBODT3 0xE679046CU -#define DBSC_D3_DBADJ0 0xE6790500U -#define DBSC_D3_DBDBICNT 0xE6790518U -#define DBSC_D3_DBDFICUPDCNF 0xE679052CU -#define DBSC_D3_DBDFICNT0 0xE6790604U -#define DBSC_D3_DBPDLK0 0xE6790620U -#define DBSC_D3_DBPDRGA0 0xE6790624U -#define DBSC_D3_DBPDRGD0 0xE6790628U -#define DBSC_D3_DBPDSTAT00 0xE6790630U -#define DBSC_D3_DBDFISTAT1 0xE6790640U -#define DBSC_D3_DBDFICNT1 0xE6790644U -#define DBSC_D3_DBPDLK1 0xE6790660U -#define DBSC_D3_DBPDRGA1 0xE6790664U -#define DBSC_D3_DBPDRGD1 0xE6790668U -#define DBSC_D3_DBDFICNT2 0xE6790684U -#define DBSC_D3_DBPDLK2 0xE67906A0U -#define DBSC_D3_DBPDRGA2 0xE67906A4U -#define DBSC_D3_DBPDRGD2 0xE67906A8U -#define DBSC_D3_DBPDSTAT20 0xE67906B0U -#define DBSC_D3_DBDFISTAT3 0xE67906C0U -#define DBSC_D3_DBDFICNT3 0xE67906C4U -#define DBSC_D3_DBPDLK3 0xE67906E0U -#define DBSC_D3_DBPDRGA3 0xE67906E4U -#define DBSC_D3_DBPDRGD3 0xE67906E8U -#define DBSC_D3_DBBUS0CNF1 0xE6790804U -#define DBSC_D3_DBCAM0CNF1 0xE6790904U -#define DBSC_D3_DBCAM0CNF2 0xE6790908U -#define DBSC_D3_DBCAM0STAT0 0xE6790980U -#define DBSC_D3_DBCAM1STAT0 0xE6790990U -#define DBSC_D3_DBBCAMDIS 0xE67909FCU -#define DBSC_D3_DBSCHCNT0 0xE6791000U -#define DBSC_D3_DBSCHSZ0 0xE6791010U -#define DBSC_D3_DBSCHRW0 0xE6791020U -#define DBSC_D3_DBSCHRW1 0xE6791024U -#define DBSC_D3_DBSCHQOS00 0xE6791030U -#define DBSC_D3_DBSCHQOS01 0xE6791034U -#define DBSC_D3_DBSCHQOS02 0xE6791038U -#define DBSC_D3_DBSCHQOS03 0xE679103CU -#define DBSC_D3_DBSCHQOS10 0xE6791040U -#define DBSC_D3_DBSCHQOS11 0xE6791044U -#define DBSC_D3_DBSCHQOS12 0xE6791048U -#define DBSC_D3_DBSCHQOS13 0xE679104CU -#define DBSC_D3_DBSCHQOS20 0xE6791050U -#define DBSC_D3_DBSCHQOS21 0xE6791054U -#define DBSC_D3_DBSCHQOS22 0xE6791058U -#define DBSC_D3_DBSCHQOS23 0xE679105CU -#define DBSC_D3_DBSCHQOS30 0xE6791060U -#define DBSC_D3_DBSCHQOS31 0xE6791064U -#define DBSC_D3_DBSCHQOS32 0xE6791068U -#define DBSC_D3_DBSCHQOS33 0xE679106CU -#define DBSC_D3_DBSCHQOS40 0xE6791070U -#define DBSC_D3_DBSCHQOS41 0xE6791074U -#define DBSC_D3_DBSCHQOS42 0xE6791078U -#define DBSC_D3_DBSCHQOS43 0xE679107CU -#define DBSC_D3_DBSCHQOS50 0xE6791080U -#define DBSC_D3_DBSCHQOS51 0xE6791084U -#define DBSC_D3_DBSCHQOS52 0xE6791088U -#define DBSC_D3_DBSCHQOS53 0xE679108CU -#define DBSC_D3_DBSCHQOS60 0xE6791090U -#define DBSC_D3_DBSCHQOS61 0xE6791094U -#define DBSC_D3_DBSCHQOS62 0xE6791098U -#define DBSC_D3_DBSCHQOS63 0xE679109CU -#define DBSC_D3_DBSCHQOS70 0xE67910A0U -#define DBSC_D3_DBSCHQOS71 0xE67910A4U -#define DBSC_D3_DBSCHQOS72 0xE67910A8U -#define DBSC_D3_DBSCHQOS73 0xE67910ACU -#define DBSC_D3_DBSCHQOS80 0xE67910B0U -#define DBSC_D3_DBSCHQOS81 0xE67910B4U -#define DBSC_D3_DBSCHQOS82 0xE67910B8U -#define DBSC_D3_DBSCHQOS83 0xE67910BCU -#define DBSC_D3_DBSCHQOS90 0xE67910C0U -#define DBSC_D3_DBSCHQOS91 0xE67910C4U -#define DBSC_D3_DBSCHQOS92 0xE67910C8U -#define DBSC_D3_DBSCHQOS93 0xE67910CCU -#define DBSC_D3_DBSCHQOS100 0xE67910D0U -#define DBSC_D3_DBSCHQOS101 0xE67910D4U -#define DBSC_D3_DBSCHQOS102 0xE67910D8U -#define DBSC_D3_DBSCHQOS103 0xE67910DCU -#define DBSC_D3_DBSCHQOS110 0xE67910E0U -#define DBSC_D3_DBSCHQOS111 0xE67910E4U -#define DBSC_D3_DBSCHQOS112 0xE67910E8U -#define DBSC_D3_DBSCHQOS113 0xE67910ECU -#define DBSC_D3_DBSCHQOS120 0xE67910F0U -#define DBSC_D3_DBSCHQOS121 0xE67910F4U -#define DBSC_D3_DBSCHQOS122 0xE67910F8U -#define DBSC_D3_DBSCHQOS123 0xE67910FCU -#define DBSC_D3_DBSCHQOS130 0xE6791100U -#define DBSC_D3_DBSCHQOS131 0xE6791104U -#define DBSC_D3_DBSCHQOS132 0xE6791108U -#define DBSC_D3_DBSCHQOS133 0xE679110CU -#define DBSC_D3_DBSCHQOS140 0xE6791110U -#define DBSC_D3_DBSCHQOS141 0xE6791114U -#define DBSC_D3_DBSCHQOS142 0xE6791118U -#define DBSC_D3_DBSCHQOS143 0xE679111CU -#define DBSC_D3_DBSCHQOS150 0xE6791120U -#define DBSC_D3_DBSCHQOS151 0xE6791124U -#define DBSC_D3_DBSCHQOS152 0xE6791128U -#define DBSC_D3_DBSCHQOS153 0xE679112CU -#define DBSC_D3_SCFCTST0 0xE6791700U -#define DBSC_D3_SCFCTST1 0xE6791708U -#define DBSC_D3_SCFCTST2 0xE679170CU -#define DBSC_D3_DBMRRDR0 0xE6791800U -#define DBSC_D3_DBMRRDR1 0xE6791804U -#define DBSC_D3_DBMRRDR2 0xE6791808U -#define DBSC_D3_DBMRRDR3 0xE679180CU -#define DBSC_D3_DBMRRDR4 0xE6791810U -#define DBSC_D3_DBMRRDR5 0xE6791814U -#define DBSC_D3_DBMRRDR6 0xE6791818U -#define DBSC_D3_DBMRRDR7 0xE679181CU - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* BOOT_INIT_DRAM_REGDEF_D3_H_*/ diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_e3.h b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_e3.h deleted file mode 100644 index 8606f76d2c..0000000000 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_e3.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef BOOT_INIT_DRAM_REGDEF_E3_H -#define BOOT_INIT_DRAM_REGDEF_E3_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define BIT0 0x00000001U -#define BIT11 0x00000800U -#define BIT30 0x40000000U - -/* DBSC registers */ - -#define DBSC_E3_DBSYSCONF1 0xE6790004U -#define DBSC_E3_DBPHYCONF0 0xE6790010U -#define DBSC_E3_DBKIND 0xE6790020U -#define DBSC_E3_DBMEMCONF00 0xE6790030U -#define DBSC_E3_DBSYSCNT0 0xE6790100U -#define DBSC_E3_DBACEN 0xE6790200U -#define DBSC_E3_DBRFEN 0xE6790204U -#define DBSC_E3_DBCMD 0xE6790208U -#define DBSC_E3_DBWAIT 0xE6790210U -#define DBSC_E3_DBTR0 0xE6790300U -#define DBSC_E3_DBTR1 0xE6790304U -#define DBSC_E3_DBTR2 0xE6790308U -#define DBSC_E3_DBTR3 0xE679030CU -#define DBSC_E3_DBTR4 0xE6790310U -#define DBSC_E3_DBTR5 0xE6790314U -#define DBSC_E3_DBTR6 0xE6790318U -#define DBSC_E3_DBTR7 0xE679031CU -#define DBSC_E3_DBTR8 0xE6790320U -#define DBSC_E3_DBTR9 0xE6790324U -#define DBSC_E3_DBTR10 0xE6790328U -#define DBSC_E3_DBTR11 0xE679032CU -#define DBSC_E3_DBTR12 0xE6790330U -#define DBSC_E3_DBTR13 0xE6790334U -#define DBSC_E3_DBTR14 0xE6790338U -#define DBSC_E3_DBTR15 0xE679033CU -#define DBSC_E3_DBTR16 0xE6790340U -#define DBSC_E3_DBTR17 0xE6790344U -#define DBSC_E3_DBTR18 0xE6790348U -#define DBSC_E3_DBTR19 0xE679034CU -#define DBSC_E3_DBTR20 0xE6790350U -#define DBSC_E3_DBTR21 0xE6790354U -#define DBSC_E3_DBBL 0xE6790400U -#define DBSC_E3_DBRFCNF1 0xE6790414U -#define DBSC_E3_DBRFCNF2 0xE6790418U -#define DBSC_E3_DBCALCNF 0xE6790424U -#define DBSC_E3_DBODT0 0xE6790460U -#define DBSC_E3_DBADJ0 0xE6790500U -#define DBSC_E3_DBDFICUPDCNF 0xE679052CU -#define DBSC_E3_DBDFICNT0 0xE6790604U -#define DBSC_E3_DBPDLK0 0xE6790620U -#define DBSC_E3_DBPDRGA0 0xE6790624U -#define DBSC_E3_DBPDRGD0 0xE6790628U -#define DBSC_E3_DBBUS0CNF1 0xE6790804U -#define DBSC_E3_DBCAM0CNF1 0xE6790904U -#define DBSC_E3_DBCAM0CNF2 0xE6790908U -#define DBSC_E3_DBCAM0STAT0 0xE6790980U -#define DBSC_E3_DBBCAMDIS 0xE67909FCU -#define DBSC_E3_DBSCHCNT0 0xE6791000U -#define DBSC_E3_DBSCHSZ0 0xE6791010U -#define DBSC_E3_DBSCHRW0 0xE6791020U -#define DBSC_E3_DBSCHRW1 0xE6791024U -#define DBSC_E3_DBSCHQOS00 0xE6791030U -#define DBSC_E3_DBSCHQOS01 0xE6791034U -#define DBSC_E3_DBSCHQOS02 0xE6791038U -#define DBSC_E3_DBSCHQOS03 0xE679103CU -#define DBSC_E3_DBSCHQOS40 0xE6791070U -#define DBSC_E3_DBSCHQOS41 0xE6791074U -#define DBSC_E3_DBSCHQOS42 0xE6791078U -#define DBSC_E3_DBSCHQOS43 0xE679107CU -#define DBSC_E3_DBSCHQOS90 0xE67910C0U -#define DBSC_E3_DBSCHQOS91 0xE67910C4U -#define DBSC_E3_DBSCHQOS92 0xE67910C8U -#define DBSC_E3_DBSCHQOS93 0xE67910CCU -#define DBSC_E3_DBSCHQOS130 0xE6791100U -#define DBSC_E3_DBSCHQOS131 0xE6791104U -#define DBSC_E3_DBSCHQOS132 0xE6791108U -#define DBSC_E3_DBSCHQOS133 0xE679110CU -#define DBSC_E3_DBSCHQOS140 0xE6791110U -#define DBSC_E3_DBSCHQOS141 0xE6791114U -#define DBSC_E3_DBSCHQOS142 0xE6791118U -#define DBSC_E3_DBSCHQOS143 0xE679111CU -#define DBSC_E3_DBSCHQOS150 0xE6791120U -#define DBSC_E3_DBSCHQOS151 0xE6791124U -#define DBSC_E3_DBSCHQOS152 0xE6791128U -#define DBSC_E3_DBSCHQOS153 0xE679112CU -#define DBSC_E3_SCFCTST0 0xE6791700U -#define DBSC_E3_SCFCTST1 0xE6791708U -#define DBSC_E3_SCFCTST2 0xE679170CU - -/* CPG registers */ - -#define CPG_SRCR4 0xE61500BCU -#define CPG_PLLECR 0xE61500D0U -#define CPG_CPGWPR 0xE6150900U -#define CPG_CPGWPCR 0xE6150904U -#define CPG_SRSTCLR4 0xE6150950U - -/* MODE Monitor registers */ - -#define RST_MODEMR 0xE6160060U - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* BOOT_INIT_DRAM_REGDEF_E3_H */ diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_v3m.h b/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_v3m.h deleted file mode 100644 index ecb8e6208b..0000000000 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef_v3m.h +++ /dev/null @@ -1,296 +0,0 @@ -/* - * Copyright (c) 2015-2016, Renesas Electronics Corporation - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef BOOT_INIT_DRAM_REGDEF_V3M_H_ -#define BOOT_INIT_DRAM_REGDEF_V3M_H_ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define BIT0 0x00000001U -#define BIT30 0x40000000U - -/* DBSC registers */ - -// modified , last 2016.12.08 - -#define DBSC_V3M_DBSYSCONF0 0xE6790000U -#define DBSC_V3M_DBSYSCONF1 0xE6790004U -#define DBSC_V3M_DBPHYCONF0 0xE6790010U -#define DBSC_V3M_DBKIND 0xE6790020U -#define DBSC_V3M_DBMEMCONF00 0xE6790030U -#define DBSC_V3M_DBMEMCONF01 0xE6790034U -#define DBSC_V3M_DBMEMCONF02 0xE6790038U -#define DBSC_V3M_DBMEMCONF03 0xE679003CU -#define DBSC_V3M_DBMEMCONF10 0xE6790040U -#define DBSC_V3M_DBMEMCONF11 0xE6790044U -#define DBSC_V3M_DBMEMCONF12 0xE6790048U -#define DBSC_V3M_DBMEMCONF13 0xE679004CU -#define DBSC_V3M_DBMEMCONF20 0xE6790050U -#define DBSC_V3M_DBMEMCONF21 0xE6790054U -#define DBSC_V3M_DBMEMCONF22 0xE6790058U -#define DBSC_V3M_DBMEMCONF23 0xE679005CU -#define DBSC_V3M_DBMEMCONF30 0xE6790060U -#define DBSC_V3M_DBMEMCONF31 0xE6790064U -#define DBSC_V3M_DBMEMCONF32 0xE6790068U -#define DBSC_V3M_DBMEMCONF33 0xE679006CU -#define DBSC_V3M_DBSYSCNT0 0xE6790100U -#define DBSC_V3M_DBSVCR1 0xE6790104U -#define DBSC_V3M_DBSTATE0 0xE6790108U -#define DBSC_V3M_DBSTATE1 0xE679010CU -#define DBSC_V3M_DBINTEN 0xE6790180U -#define DBSC_V3M_DBINTSTAT0 0xE6790184U -#define DBSC_V3M_DBACEN 0xE6790200U -#define DBSC_V3M_DBRFEN 0xE6790204U -#define DBSC_V3M_DBCMD 0xE6790208U -#define DBSC_V3M_DBWAIT 0xE6790210U -#define DBSC_V3M_DBSYSCTRL0 0xE6790280U -#define DBSC_V3M_DBTR0 0xE6790300U -#define DBSC_V3M_DBTR1 0xE6790304U -#define DBSC_V3M_DBTR2 0xE6790308U -#define DBSC_V3M_DBTR3 0xE679030CU -#define DBSC_V3M_DBTR4 0xE6790310U -#define DBSC_V3M_DBTR5 0xE6790314U -#define DBSC_V3M_DBTR6 0xE6790318U -#define DBSC_V3M_DBTR7 0xE679031CU -#define DBSC_V3M_DBTR8 0xE6790320U -#define DBSC_V3M_DBTR9 0xE6790324U -#define DBSC_V3M_DBTR10 0xE6790328U -#define DBSC_V3M_DBTR11 0xE679032CU -#define DBSC_V3M_DBTR12 0xE6790330U -#define DBSC_V3M_DBTR13 0xE6790334U -#define DBSC_V3M_DBTR14 0xE6790338U -#define DBSC_V3M_DBTR15 0xE679033CU -#define DBSC_V3M_DBTR16 0xE6790340U -#define DBSC_V3M_DBTR17 0xE6790344U -#define DBSC_V3M_DBTR18 0xE6790348U -#define DBSC_V3M_DBTR19 0xE679034CU -#define DBSC_V3M_DBTR20 0xE6790350U -#define DBSC_V3M_DBTR21 0xE6790354U -#define DBSC_V3M_DBTR22 0xE6790358U -#define DBSC_V3M_DBTR23 0xE679035CU -#define DBSC_V3M_DBTR24 0xE6790360U -#define DBSC_V3M_DBTR25 0xE6790364U -#define DBSC_V3M_DBBL 0xE6790400U -#define DBSC_V3M_DBRFCNF1 0xE6790414U -#define DBSC_V3M_DBRFCNF2 0xE6790418U -#define DBSC_V3M_DBTSPCNF 0xE6790420U -#define DBSC_V3M_DBCALCNF 0xE6790424U -#define DBSC_V3M_DBRNK2 0xE6790438U -#define DBSC_V3M_DBRNK3 0xE679043CU -#define DBSC_V3M_DBRNK4 0xE6790440U -#define DBSC_V3M_DBRNK5 0xE6790444U -#define DBSC_V3M_DBPDNCNF 0xE6790450U -#define DBSC_V3M_DBODT0 0xE6790460U -#define DBSC_V3M_DBODT1 0xE6790464U -#define DBSC_V3M_DBODT2 0xE6790468U -#define DBSC_V3M_DBODT3 0xE679046CU -#define DBSC_V3M_DBODT4 0xE6790470U -#define DBSC_V3M_DBODT5 0xE6790474U -#define DBSC_V3M_DBODT6 0xE6790478U -#define DBSC_V3M_DBODT7 0xE679047CU -#define DBSC_V3M_DBADJ0 0xE6790500U -#define DBSC_V3M_DBDBICNT 0xE6790518U -#define DBSC_V3M_DBDFIPMSTRCNF 0xE6790520U -#define DBSC_V3M_DBDFIPMSTRSTAT 0xE6790524U -#define DBSC_V3M_DBDFILPCNF 0xE6790528U -#define DBSC_V3M_DBDFICUPDCNF 0xE679052CU -#define DBSC_V3M_DBDFISTAT0 0xE6790600U -#define DBSC_V3M_DBDFICNT0 0xE6790604U -#define DBSC_V3M_DBPDCNT00 0xE6790610U -#define DBSC_V3M_DBPDCNT01 0xE6790614U -#define DBSC_V3M_DBPDCNT02 0xE6790618U -#define DBSC_V3M_DBPDCNT03 0xE679061CU -#define DBSC_V3M_DBPDLK0 0xE6790620U -#define DBSC_V3M_DBPDRGA0 0xE6790624U -#define DBSC_V3M_DBPDRGD0 0xE6790628U -#define DBSC_V3M_DBPDSTAT00 0xE6790630U -#define DBSC_V3M_DBDFISTAT1 0xE6790640U -#define DBSC_V3M_DBDFICNT1 0xE6790644U -#define DBSC_V3M_DBPDCNT10 0xE6790650U -#define DBSC_V3M_DBPDCNT11 0xE6790654U -#define DBSC_V3M_DBPDCNT12 0xE6790658U -#define DBSC_V3M_DBPDCNT13 0xE679065CU -#define DBSC_V3M_DBPDLK1 0xE6790660U -#define DBSC_V3M_DBPDRGA1 0xE6790664U -#define DBSC_V3M_DBPDRGD1 0xE6790668U -#define DBSC_V3M_DBPDSTAT10 0xE6790670U -#define DBSC_V3M_DBDFISTAT2 0xE6790680U -#define DBSC_V3M_DBDFICNT2 0xE6790684U -#define DBSC_V3M_DBPDCNT20 0xE6790690U -#define DBSC_V3M_DBPDCNT21 0xE6790694U -#define DBSC_V3M_DBPDCNT22 0xE6790698U -#define DBSC_V3M_DBPDCNT23 0xE679069CU -#define DBSC_V3M_DBPDLK2 0xE67906A0U -#define DBSC_V3M_DBPDRGA2 0xE67906A4U -#define DBSC_V3M_DBPDRGD2 0xE67906A8U -#define DBSC_V3M_DBPDSTAT20 0xE67906B0U -#define DBSC_V3M_DBDFISTAT3 0xE67906C0U -#define DBSC_V3M_DBDFICNT3 0xE67906C4U -#define DBSC_V3M_DBPDCNT30 0xE67906D0U -#define DBSC_V3M_DBPDCNT31 0xE67906D4U -#define DBSC_V3M_DBPDCNT32 0xE67906D8U -#define DBSC_V3M_DBPDCNT33 0xE67906DCU -#define DBSC_V3M_DBPDLK3 0xE67906E0U -#define DBSC_V3M_DBPDRGA3 0xE67906E4U -#define DBSC_V3M_DBPDRGD3 0xE67906E8U -#define DBSC_V3M_DBPDSTAT30 0xE67906F0U -#define DBSC_V3M_DBBUS0CNF0 0xE6790800U -#define DBSC_V3M_DBBUS0CNF1 0xE6790804U -#define DBSC_V3M_DBCAM0CNF1 0xE6790904U -#define DBSC_V3M_DBCAM0CNF2 0xE6790908U -#define DBSC_V3M_DBCAM0CNF3 0xE679090CU -#define DBSC_V3M_DBCAM0CTRL0 0xE6790940U -#define DBSC_V3M_DBCAM0STAT0 0xE6790980U -#define DBSC_V3M_DBCAM1STAT0 0xE6790990U -#define DBSC_V3M_DBBCAMSWAP 0xE67909F0U -#define DBSC_V3M_DBBCAMDIS 0xE67909FCU -#define DBSC_V3M_DBSCHCNT0 0xE6791000U -#define DBSC_V3M_DBSCHCNT1 0xE6791004U -#define DBSC_V3M_DBSCHSZ0 0xE6791010U -#define DBSC_V3M_DBSCHRW0 0xE6791020U -#define DBSC_V3M_DBSCHRW1 0xE6791024U -#define DBSC_V3M_DBSCHQOS00 0xE6791030U -#define DBSC_V3M_DBSCHQOS01 0xE6791034U -#define DBSC_V3M_DBSCHQOS02 0xE6791038U -#define DBSC_V3M_DBSCHQOS03 0xE679103CU -#define DBSC_V3M_DBSCHQOS10 0xE6791040U -#define DBSC_V3M_DBSCHQOS11 0xE6791044U -#define DBSC_V3M_DBSCHQOS12 0xE6791048U -#define DBSC_V3M_DBSCHQOS13 0xE679104CU -#define DBSC_V3M_DBSCHQOS20 0xE6791050U -#define DBSC_V3M_DBSCHQOS21 0xE6791054U -#define DBSC_V3M_DBSCHQOS22 0xE6791058U -#define DBSC_V3M_DBSCHQOS23 0xE679105CU -#define DBSC_V3M_DBSCHQOS30 0xE6791060U -#define DBSC_V3M_DBSCHQOS31 0xE6791064U -#define DBSC_V3M_DBSCHQOS32 0xE6791068U -#define DBSC_V3M_DBSCHQOS33 0xE679106CU -#define DBSC_V3M_DBSCHQOS40 0xE6791070U -#define DBSC_V3M_DBSCHQOS41 0xE6791074U -#define DBSC_V3M_DBSCHQOS42 0xE6791078U -#define DBSC_V3M_DBSCHQOS43 0xE679107CU -#define DBSC_V3M_DBSCHQOS50 0xE6791080U -#define DBSC_V3M_DBSCHQOS51 0xE6791084U -#define DBSC_V3M_DBSCHQOS52 0xE6791088U -#define DBSC_V3M_DBSCHQOS53 0xE679108CU -#define DBSC_V3M_DBSCHQOS60 0xE6791090U -#define DBSC_V3M_DBSCHQOS61 0xE6791094U -#define DBSC_V3M_DBSCHQOS62 0xE6791098U -#define DBSC_V3M_DBSCHQOS63 0xE679109CU -#define DBSC_V3M_DBSCHQOS70 0xE67910A0U -#define DBSC_V3M_DBSCHQOS71 0xE67910A4U -#define DBSC_V3M_DBSCHQOS72 0xE67910A8U -#define DBSC_V3M_DBSCHQOS73 0xE67910ACU -#define DBSC_V3M_DBSCHQOS80 0xE67910B0U -#define DBSC_V3M_DBSCHQOS81 0xE67910B4U -#define DBSC_V3M_DBSCHQOS82 0xE67910B8U -#define DBSC_V3M_DBSCHQOS83 0xE67910BCU -#define DBSC_V3M_DBSCHQOS90 0xE67910C0U -#define DBSC_V3M_DBSCHQOS91 0xE67910C4U -#define DBSC_V3M_DBSCHQOS92 0xE67910C8U -#define DBSC_V3M_DBSCHQOS93 0xE67910CCU -#define DBSC_V3M_DBSCHQOS100 0xE67910D0U -#define DBSC_V3M_DBSCHQOS101 0xE67910D4U -#define DBSC_V3M_DBSCHQOS102 0xE67910D8U -#define DBSC_V3M_DBSCHQOS103 0xE67910DCU -#define DBSC_V3M_DBSCHQOS110 0xE67910E0U -#define DBSC_V3M_DBSCHQOS111 0xE67910E4U -#define DBSC_V3M_DBSCHQOS112 0xE67910E8U -#define DBSC_V3M_DBSCHQOS113 0xE67910ECU -#define DBSC_V3M_DBSCHQOS120 0xE67910F0U -#define DBSC_V3M_DBSCHQOS121 0xE67910F4U -#define DBSC_V3M_DBSCHQOS122 0xE67910F8U -#define DBSC_V3M_DBSCHQOS123 0xE67910FCU -#define DBSC_V3M_DBSCHQOS130 0xE6791100U -#define DBSC_V3M_DBSCHQOS131 0xE6791104U -#define DBSC_V3M_DBSCHQOS132 0xE6791108U -#define DBSC_V3M_DBSCHQOS133 0xE679110CU -#define DBSC_V3M_DBSCHQOS140 0xE6791110U -#define DBSC_V3M_DBSCHQOS141 0xE6791114U -#define DBSC_V3M_DBSCHQOS142 0xE6791118U -#define DBSC_V3M_DBSCHQOS143 0xE679111CU -#define DBSC_V3M_DBSCHQOS150 0xE6791120U -#define DBSC_V3M_DBSCHQOS151 0xE6791124U -#define DBSC_V3M_DBSCHQOS152 0xE6791128U -#define DBSC_V3M_DBSCHQOS153 0xE679112CU -#define DBSC_V3M_SCFCTST0 0xE6791700U -#define DBSC_V3M_SCFCTST1 0xE6791708U -#define DBSC_V3M_SCFCTST2 0xE679170CU -#define DBSC_V3M_DBMRRDR0 0xE6791800U -#define DBSC_V3M_DBMRRDR1 0xE6791804U -#define DBSC_V3M_DBMRRDR2 0xE6791808U -#define DBSC_V3M_DBMRRDR3 0xE679180CU -#define DBSC_V3M_DBMRRDR4 0xE6791810U -#define DBSC_V3M_DBMRRDR5 0xE6791814U -#define DBSC_V3M_DBMRRDR6 0xE6791818U -#define DBSC_V3M_DBMRRDR7 0xE679181CU -#define DBSC_V3M_DBDTMP0 0xE6791820U -#define DBSC_V3M_DBDTMP1 0xE6791824U -#define DBSC_V3M_DBDTMP2 0xE6791828U -#define DBSC_V3M_DBDTMP3 0xE679182CU -#define DBSC_V3M_DBDTMP4 0xE6791830U -#define DBSC_V3M_DBDTMP5 0xE6791834U -#define DBSC_V3M_DBDTMP6 0xE6791838U -#define DBSC_V3M_DBDTMP7 0xE679183CU -#define DBSC_V3M_DBDQSOSC00 0xE6791840U -#define DBSC_V3M_DBDQSOSC01 0xE6791844U -#define DBSC_V3M_DBDQSOSC10 0xE6791848U -#define DBSC_V3M_DBDQSOSC11 0xE679184CU -#define DBSC_V3M_DBDQSOSC20 0xE6791850U -#define DBSC_V3M_DBDQSOSC21 0xE6791854U -#define DBSC_V3M_DBDQSOSC30 0xE6791858U -#define DBSC_V3M_DBDQSOSC31 0xE679185CU -#define DBSC_V3M_DBDQSOSC40 0xE6791860U -#define DBSC_V3M_DBDQSOSC41 0xE6791864U -#define DBSC_V3M_DBDQSOSC50 0xE6791868U -#define DBSC_V3M_DBDQSOSC51 0xE679186CU -#define DBSC_V3M_DBDQSOSC60 0xE6791870U -#define DBSC_V3M_DBDQSOSC61 0xE6791874U -#define DBSC_V3M_DBDQSOSC70 0xE6791878U -#define DBSC_V3M_DBDQSOSC71 0xE679187CU -#define DBSC_V3M_DBOSCTHH00 0xE6791880U -#define DBSC_V3M_DBOSCTHH01 0xE6791884U -#define DBSC_V3M_DBOSCTHH10 0xE6791888U -#define DBSC_V3M_DBOSCTHH11 0xE679188CU -#define DBSC_V3M_DBOSCTHH20 0xE6791890U -#define DBSC_V3M_DBOSCTHH21 0xE6791894U -#define DBSC_V3M_DBOSCTHH30 0xE6791898U -#define DBSC_V3M_DBOSCTHH31 0xE679189CU -#define DBSC_V3M_DBOSCTHH40 0xE67918A0U -#define DBSC_V3M_DBOSCTHH41 0xE67918A4U -#define DBSC_V3M_DBOSCTHH50 0xE67918A8U -#define DBSC_V3M_DBOSCTHH51 0xE67918ACU -#define DBSC_V3M_DBOSCTHH60 0xE67918B0U -#define DBSC_V3M_DBOSCTHH61 0xE67918B4U -#define DBSC_V3M_DBOSCTHH70 0xE67918B8U -#define DBSC_V3M_DBOSCTHH71 0xE67918BCU -#define DBSC_V3M_DBOSCTHL00 0xE67918C0U -#define DBSC_V3M_DBOSCTHL01 0xE67918C4U -#define DBSC_V3M_DBOSCTHL10 0xE67918C8U -#define DBSC_V3M_DBOSCTHL11 0xE67918CCU -#define DBSC_V3M_DBOSCTHL20 0xE67918D0U -#define DBSC_V3M_DBOSCTHL21 0xE67918D4U -#define DBSC_V3M_DBOSCTHL30 0xE67918D8U -#define DBSC_V3M_DBOSCTHL31 0xE67918DCU -#define DBSC_V3M_DBOSCTHL40 0xE67918E0U -#define DBSC_V3M_DBOSCTHL41 0xE67918E4U -#define DBSC_V3M_DBOSCTHL50 0xE67918E8U -#define DBSC_V3M_DBOSCTHL51 0xE67918ECU -#define DBSC_V3M_DBOSCTHL60 0xE67918F0U -#define DBSC_V3M_DBOSCTHL61 0xE67918F4U -#define DBSC_V3M_DBOSCTHL70 0xE67918F8U -#define DBSC_V3M_DBOSCTHL71 0xE67918FCU -#define DBSC_V3M_DBMEMSWAPCONF0 0xE6792000U - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* BOOT_INIT_DRAM_REGDEF_V3M_H_*/ diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c index 9a9d06aebe..d03b1b965a 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_d3.c @@ -1,5 +1,6 @@ /* - * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,660 +9,668 @@ #include <lib/mmio.h> #include <common/debug.h> -#include "boot_init_dram_regdef_d3.h" +#include "boot_init_dram_regdef.h" -#define RCAR_DDR_VERSION "rev.0.01" +#define RCAR_DDR_VERSION "rev.0.01" #if RCAR_LSI != RCAR_D3 #error "Don't have DDR initialize routine." #endif -static void WriteReg_32(uint32_t a, uint32_t v) +static void init_ddr_d3_1866(void) { - (*(volatile uint32_t*)(uintptr_t)a) = v; -} + uint32_t i, r2, r3, r5, r6, r7, r12; + + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + mmio_write_32(DBSC_DBKIND, 0x00000007); + mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a01); + mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); + mmio_write_32(DBSC_DBTR0, 0x0000000D); + mmio_write_32(DBSC_DBTR1, 0x00000009); + mmio_write_32(DBSC_DBTR2, 0x00000000); + mmio_write_32(DBSC_DBTR3, 0x0000000D); + mmio_write_32(DBSC_DBTR4, 0x000D000D); + mmio_write_32(DBSC_DBTR5, 0x0000002D); + mmio_write_32(DBSC_DBTR6, 0x00000020); + mmio_write_32(DBSC_DBTR7, 0x00060006); + mmio_write_32(DBSC_DBTR8, 0x00000021); + mmio_write_32(DBSC_DBTR9, 0x00000007); + mmio_write_32(DBSC_DBTR10, 0x0000000E); + mmio_write_32(DBSC_DBTR11, 0x0000000C); + mmio_write_32(DBSC_DBTR12, 0x00140014); + mmio_write_32(DBSC_DBTR13, 0x000000F2); + mmio_write_32(DBSC_DBTR14, 0x00170006); + mmio_write_32(DBSC_DBTR15, 0x00060005); + mmio_write_32(DBSC_DBTR16, 0x09210507); + mmio_write_32(DBSC_DBTR17, 0x040E0000); + mmio_write_32(DBSC_DBTR18, 0x00000200); + mmio_write_32(DBSC_DBTR19, 0x012B004B); + mmio_write_32(DBSC_DBTR20, 0x020000FB); + mmio_write_32(DBSC_DBTR21, 0x00040004); + mmio_write_32(DBSC_DBBL, 0x00000000); + mmio_write_32(DBSC_DBODT0, 0x00000001); + mmio_write_32(DBSC_DBADJ0, 0x00000001); + mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); + mmio_write_32(DBSC_DBDFICNT0, 0x00000010); + mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); + mmio_write_32(DBSC_DBSCHRW1, 0x00000046); + mmio_write_32(DBSC_SCFCTST0, 0x0D020D04); + mmio_write_32(DBSC_SCFCTST1, 0x0306040C); + + mmio_write_32(DBSC_DBPDLK0, 0x0000A55A); + mmio_write_32(DBSC_DBCMD, 0x01000001); + mmio_write_32(DBSC_DBCMD, 0x08000000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x80010000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000008); + mmio_write_32(DBSC_DBPDRGD0, 0x000B8000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD0, 0x04058A04); + mmio_write_32(DBSC_DBPDRGA0, 0x00000091); + mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA0, 0x00000095); + mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD); + mmio_write_32(DBSC_DBPDRGA0, 0x00000099); + mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD0, 0x04058A00); + mmio_write_32(DBSC_DBPDRGA0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD0, 0x0024641E); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010073); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00); + mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD0, 0x04058A00); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD0, 0x0780C700); + mmio_write_32(DBSC_DBPDRGA0, 0x00000007); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000004); + mmio_write_32(DBSC_DBPDRGD0, 0x0A206F89); + mmio_write_32(DBSC_DBPDRGA0, 0x00000022); + mmio_write_32(DBSC_DBPDRGD0, 0x1000040B); + mmio_write_32(DBSC_DBPDRGA0, 0x00000023); + mmio_write_32(DBSC_DBPDRGD0, 0x35A00D77); + mmio_write_32(DBSC_DBPDRGA0, 0x00000024); + mmio_write_32(DBSC_DBPDRGD0, 0x2A8A2C28); + mmio_write_32(DBSC_DBPDRGA0, 0x00000025); + mmio_write_32(DBSC_DBPDRGD0, 0x30005E00); + mmio_write_32(DBSC_DBPDRGA0, 0x00000026); + mmio_write_32(DBSC_DBPDRGD0, 0x0014CB49); + mmio_write_32(DBSC_DBPDRGA0, 0x00000027); + mmio_write_32(DBSC_DBPDRGD0, 0x00000F14); + mmio_write_32(DBSC_DBPDRGA0, 0x00000028); + mmio_write_32(DBSC_DBPDRGD0, 0x00000046); + mmio_write_32(DBSC_DBPDRGA0, 0x00000029); + mmio_write_32(DBSC_DBPDRGD0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD0, 0x81003047); + mmio_write_32(DBSC_DBPDRGA0, 0x00000020); + mmio_write_32(DBSC_DBPDRGD0, 0x00181884); + mmio_write_32(DBSC_DBPDRGA0, 0x0000001A); + mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x000000A7); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000A8); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000A9); + mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C7); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C8); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C9); + mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); + + mmio_write_32(DBSC_DBPDRGA0, 0x0000000E); + r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x9; + r3 = (r2 << 16) + (r2 << 8) + r2; + r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2; + mmio_write_32(DBSC_DBPDRGA0, 0x00000011); + mmio_write_32(DBSC_DBPDRGD0, r3); + mmio_write_32(DBSC_DBPDRGA0, 0x00000012); + mmio_write_32(DBSC_DBPDRGD0, r3); + mmio_write_32(DBSC_DBPDRGA0, 0x00000016); + mmio_write_32(DBSC_DBPDRGD0, r6); + mmio_write_32(DBSC_DBPDRGA0, 0x00000017); + mmio_write_32(DBSC_DBPDRGD0, r6); + mmio_write_32(DBSC_DBPDRGA0, 0x00000018); + mmio_write_32(DBSC_DBPDRGD0, r6); + mmio_write_32(DBSC_DBPDRGA0, 0x00000019); + mmio_write_32(DBSC_DBPDRGD0, r6); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010181); + mmio_write_32(DBSC_DBCMD, 0x08000001); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010601); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + for (i = 0; i < 2; i++) { + mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8; + mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + + if (r6 > 0) { + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; + + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | r6); + } else { + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | r7); + + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | + ((r6 + (r5 << 1)) & 0xFF)); + } + } -static uint32_t ReadReg_32(uint32_t a) -{ - uint32_t w = (*(volatile uint32_t*)(uintptr_t)a); - return w; -} + mmio_write_32(DBSC_DBPDRGA0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0); + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010801); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x0001F001); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x000000AF); + r2 = mmio_read_32(DBSC_DBPDRGD0); + mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); + mmio_write_32(DBSC_DBPDRGA0, 0x000000CF); + r2 = mmio_read_32(DBSC_DBPDRGD0); + mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); + + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD0, 0x81003087); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010401); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + for (i = 0; i < 2; i++) { + mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); + r5 = ((mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8); + mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; + + mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + r12 = (r5 >> 0x2); + + if (r12 < r6) { + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; + + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; + + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF)); + } else { + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7)); + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | + ((r6 + r5 + + (r5 >> 1) + r12) & 0xFF)); + } + } -static void init_ddr_d3_1866(void) -{ - uint32_t RegVal_R2, RegVal_R3, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12; - - WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234); - WriteReg_32(DBSC_D3_DBKIND,0x00000007); - WriteReg_32(DBSC_D3_DBMEMCONF00,0x0f030a01); - WriteReg_32(DBSC_D3_DBPHYCONF0,0x00000001); - WriteReg_32(DBSC_D3_DBTR0,0x0000000D); - WriteReg_32(DBSC_D3_DBTR1,0x00000009); - WriteReg_32(DBSC_D3_DBTR2,0x00000000); - WriteReg_32(DBSC_D3_DBTR3,0x0000000D); - WriteReg_32(DBSC_D3_DBTR4,0x000D000D); - WriteReg_32(DBSC_D3_DBTR5,0x0000002D); - WriteReg_32(DBSC_D3_DBTR6,0x00000020); - WriteReg_32(DBSC_D3_DBTR7,0x00060006); - WriteReg_32(DBSC_D3_DBTR8,0x00000021); - WriteReg_32(DBSC_D3_DBTR9,0x00000007); - WriteReg_32(DBSC_D3_DBTR10,0x0000000E); - WriteReg_32(DBSC_D3_DBTR11,0x0000000C); - WriteReg_32(DBSC_D3_DBTR12,0x00140014); - WriteReg_32(DBSC_D3_DBTR13,0x000000F2); - WriteReg_32(DBSC_D3_DBTR14,0x00170006); - WriteReg_32(DBSC_D3_DBTR15,0x00060005); - WriteReg_32(DBSC_D3_DBTR16,0x09210507); - WriteReg_32(DBSC_D3_DBTR17,0x040E0000); - WriteReg_32(DBSC_D3_DBTR18,0x00000200); - WriteReg_32(DBSC_D3_DBTR19,0x012B004B); - WriteReg_32(DBSC_D3_DBTR20,0x020000FB); - WriteReg_32(DBSC_D3_DBTR21,0x00040004); - WriteReg_32(DBSC_D3_DBBL,0x00000000); - WriteReg_32(DBSC_D3_DBODT0,0x00000001); - WriteReg_32(DBSC_D3_DBADJ0,0x00000001); - WriteReg_32(DBSC_D3_DBSYSCONF1,0x00000002); - WriteReg_32(DBSC_D3_DBDFICNT0,0x00000010); - WriteReg_32(DBSC_D3_DBBCAMDIS,0x00000001); - WriteReg_32(DBSC_D3_DBSCHRW1,0x00000046); - WriteReg_32(DBSC_D3_SCFCTST0,0x0D020D04); - WriteReg_32(DBSC_D3_SCFCTST1,0x0306040C); - - WriteReg_32(DBSC_D3_DBPDLK0,0x0000A55A); - WriteReg_32(DBSC_D3_DBCMD,0x01000001); - WriteReg_32(DBSC_D3_DBCMD,0x08000000); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); - WriteReg_32(DBSC_D3_DBPDRGD0,0x80010000); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); - while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000008); - WriteReg_32(DBSC_D3_DBPDRGD0,0x000B8000); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090); - WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A04); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000091); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000095); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BBAD); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000099); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090); - WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A00); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0024641E); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); - WriteReg_32(DBSC_D3_DBPDRGD0,0x00010073); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); - while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0C058A00); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090); - WriteReg_32(DBSC_D3_DBPDRGD0,0x04058A00); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); - while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0780C700); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007); - while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000004); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0A206F89); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000022); - WriteReg_32(DBSC_D3_DBPDRGD0,0x1000040B); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000023); - WriteReg_32(DBSC_D3_DBPDRGD0,0x35A00D77); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000024); - WriteReg_32(DBSC_D3_DBPDRGD0,0x2A8A2C28); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000025); - WriteReg_32(DBSC_D3_DBPDRGD0,0x30005E00); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000026); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0014CB49); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000027); - WriteReg_32(DBSC_D3_DBPDRGD0,0x00000F14); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000028); - WriteReg_32(DBSC_D3_DBPDRGD0,0x00000046); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000029); - WriteReg_32(DBSC_D3_DBPDRGD0,0x000000A0); - WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C); - WriteReg_32(DBSC_D3_DBPDRGD0,0x81003047); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000020); - WriteReg_32(DBSC_D3_DBPDRGD0,0x00181884); - WriteReg_32(DBSC_D3_DBPDRGA0,0x0000001A); - WriteReg_32(DBSC_D3_DBPDRGD0,0x33C03C10); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); - while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A7); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A8); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A9); - WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C7); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C8); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C9); - WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x0000000E); - RegVal_R2 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8) >> 0x1; - RegVal_R3 = (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2; - RegVal_R6 = (RegVal_R2 << 24) + (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2; - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000011); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000012); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000016); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000017); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000018); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000019); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); - WriteReg_32(DBSC_D3_DBPDRGD0,0x00010181); - WriteReg_32(DBSC_D3_DBCMD,0x08000001); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); - while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); - WriteReg_32(DBSC_D3_DBPDRGD0,0x00010601); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); - while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - for (uint32_t i = 0; i<2; i++) - { - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20); - RegVal_R5 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8; - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20); - RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20); - RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007); - if ( RegVal_R6 > 0 ) - { - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R6); - } else - { - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R7); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF)); - } - } - - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005); - WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00C0); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0); - WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0); - WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); - WriteReg_32(DBSC_D3_DBPDRGD0,0x00010801); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); - while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005); - WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00D8); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0001F001); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); - while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000AF); - RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0); - WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00))); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000CF); - RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0); - WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00))); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0); - WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0); - WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285); - WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C); - WriteReg_32(DBSC_D3_DBPDRGD0,0x81003087); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); - WriteReg_32(DBSC_D3_DBPDRGD0,0x00010401); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); - while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - for (uint32_t i = 0; i < 2; i++) - { - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20); - RegVal_R5 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20); - RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20); - RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007); - RegVal_R12 = (RegVal_R5 >> 0x2); - if ( RegVal_R12 < RegVal_R6 ) - { - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF)); - } - else - { - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007)); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF)); - } - } - - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0); - WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0); - WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); - WriteReg_32(DBSC_D3_DBPDRGD0,0x00015001); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); - while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0380C700); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007); - while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) != 0 ); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0024643E); - - WriteReg_32(DBSC_D3_DBBUS0CNF1,0x00000010); - WriteReg_32(DBSC_D3_DBCALCNF,0x0100401B); - WriteReg_32(DBSC_D3_DBRFCNF1,0x00080E23); - WriteReg_32(DBSC_D3_DBRFCNF2,0x00010000); - WriteReg_32(DBSC_D3_DBDFICUPDCNF,0x40100001); - WriteReg_32(DBSC_D3_DBRFEN,0x00000001); - WriteReg_32(DBSC_D3_DBACEN,0x00000001); - WriteReg_32(DBSC_D3_DBPDLK0,0x00000000); - WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000); + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00015001); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD0, 0x0380C700); + mmio_write_32(DBSC_DBPDRGA0, 0x00000007); + while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30)) + ; + mmio_write_32(DBSC_DBPDRGA0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD0, 0x0024643E); + + mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); + mmio_write_32(DBSC_DBCALCNF, 0x0100401B); + mmio_write_32(DBSC_DBRFCNF1, 0x00080E23); + mmio_write_32(DBSC_DBRFCNF2, 0x00010000); + mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); + mmio_write_32(DBSC_DBRFEN, 0x00000001); + mmio_write_32(DBSC_DBACEN, 0x00000001); + mmio_write_32(DBSC_DBPDLK0, 0x00000000); + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); #ifdef ddr_qos_init_setting // only for non qos_init - WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234); - WriteReg_32(DBSC_D3_DBCAM0CNF1,0x00043218); - WriteReg_32(DBSC_D3_DBCAM0CNF2,0x000000F4); - WriteReg_32(DBSC_D3_DBSCHCNT0,0x000f0037); - WriteReg_32(DBSC_D3_DBSCHSZ0,0x00000001); - WriteReg_32(DBSC_D3_DBSCHRW0,0x22421111); - WriteReg_32(DBSC_D3_SCFCTST2,0x012F1123); - WriteReg_32(DBSC_D3_DBSCHQOS00,0x00000F00); - WriteReg_32(DBSC_D3_DBSCHQOS01,0x00000B00); - WriteReg_32(DBSC_D3_DBSCHQOS02,0x00000000); - WriteReg_32(DBSC_D3_DBSCHQOS03,0x00000000); - WriteReg_32(DBSC_D3_DBSCHQOS40,0x00000300); - WriteReg_32(DBSC_D3_DBSCHQOS41,0x000002F0); - WriteReg_32(DBSC_D3_DBSCHQOS42,0x00000200); - WriteReg_32(DBSC_D3_DBSCHQOS43,0x00000100); - WriteReg_32(DBSC_D3_DBSCHQOS90,0x00000300); - WriteReg_32(DBSC_D3_DBSCHQOS91,0x000002F0); - WriteReg_32(DBSC_D3_DBSCHQOS92,0x00000200); - WriteReg_32(DBSC_D3_DBSCHQOS93,0x00000100); - WriteReg_32(DBSC_D3_DBSCHQOS130,0x00000100); - WriteReg_32(DBSC_D3_DBSCHQOS131,0x000000F0); - WriteReg_32(DBSC_D3_DBSCHQOS132,0x000000A0); - WriteReg_32(DBSC_D3_DBSCHQOS133,0x00000040); - WriteReg_32(DBSC_D3_DBSCHQOS140,0x000000C0); - WriteReg_32(DBSC_D3_DBSCHQOS141,0x000000B0); - WriteReg_32(DBSC_D3_DBSCHQOS142,0x00000080); - WriteReg_32(DBSC_D3_DBSCHQOS143,0x00000040); - WriteReg_32(DBSC_D3_DBSCHQOS150,0x00000040); - WriteReg_32(DBSC_D3_DBSCHQOS151,0x00000030); - WriteReg_32(DBSC_D3_DBSCHQOS152,0x00000020); - WriteReg_32(DBSC_D3_DBSCHQOS153,0x00000010); - WriteReg_32(0xE67F0018,0x00000001); - WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000); + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); + mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4); + mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037); + mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); + mmio_write_32(DBSC_DBSCHRW0, 0x22421111); + mmio_write_32(DBSC_SCFCTST2, 0x012F1123); + mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00); + mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00); + mmio_write_32(DBSC_DBSCHQOS02, 0x00000000); + mmio_write_32(DBSC_DBSCHQOS03, 0x00000000); + mmio_write_32(DBSC_DBSCHQOS40, 0x00000300); + mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0); + mmio_write_32(DBSC_DBSCHQOS42, 0x00000200); + mmio_write_32(DBSC_DBSCHQOS43, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS90, 0x00000300); + mmio_write_32(DBSC_DBSCHQOS91, 0x000002F0); + mmio_write_32(DBSC_DBSCHQOS92, 0x00000200); + mmio_write_32(DBSC_DBSCHQOS93, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS130, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0); + mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0); + mmio_write_32(DBSC_DBSCHQOS133, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0); + mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0); + mmio_write_32(DBSC_DBSCHQOS142, 0x00000080); + mmio_write_32(DBSC_DBSCHQOS143, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS150, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS151, 0x00000030); + mmio_write_32(DBSC_DBSCHQOS152, 0x00000020); + mmio_write_32(DBSC_DBSCHQOS153, 0x00000010); + mmio_write_32(0xE67F0018, 0x00000001); + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); #endif } static void init_ddr_d3_1600(void) { - uint32_t RegVal_R2, RegVal_R3, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12; - - WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234); - WriteReg_32(DBSC_D3_DBKIND,0x00000007); - WriteReg_32(DBSC_D3_DBMEMCONF00,0x0f030a01); - WriteReg_32(DBSC_D3_DBPHYCONF0,0x00000001); - WriteReg_32(DBSC_D3_DBTR0,0x0000000B); - WriteReg_32(DBSC_D3_DBTR1,0x00000008); - WriteReg_32(DBSC_D3_DBTR2,0x00000000); - WriteReg_32(DBSC_D3_DBTR3,0x0000000B); - WriteReg_32(DBSC_D3_DBTR4,0x000B000B); - WriteReg_32(DBSC_D3_DBTR5,0x00000027); - WriteReg_32(DBSC_D3_DBTR6,0x0000001C); - WriteReg_32(DBSC_D3_DBTR7,0x00060006); - WriteReg_32(DBSC_D3_DBTR8,0x00000020); - WriteReg_32(DBSC_D3_DBTR9,0x00000006); - WriteReg_32(DBSC_D3_DBTR10,0x0000000C); - WriteReg_32(DBSC_D3_DBTR11,0x0000000A); - WriteReg_32(DBSC_D3_DBTR12,0x00120012); - WriteReg_32(DBSC_D3_DBTR13,0x000000D0); - WriteReg_32(DBSC_D3_DBTR14,0x00140005); - WriteReg_32(DBSC_D3_DBTR15,0x00050004); - WriteReg_32(DBSC_D3_DBTR16,0x071F0305); - WriteReg_32(DBSC_D3_DBTR17,0x040C0000); - WriteReg_32(DBSC_D3_DBTR18,0x00000200); - WriteReg_32(DBSC_D3_DBTR19,0x01000040); - WriteReg_32(DBSC_D3_DBTR20,0x020000D8); - WriteReg_32(DBSC_D3_DBTR21,0x00040004); - WriteReg_32(DBSC_D3_DBBL,0x00000000); - WriteReg_32(DBSC_D3_DBODT0,0x00000001); - WriteReg_32(DBSC_D3_DBADJ0,0x00000001); - WriteReg_32(DBSC_D3_DBSYSCONF1,0x00000002); - WriteReg_32(DBSC_D3_DBDFICNT0,0x00000010); - WriteReg_32(DBSC_D3_DBBCAMDIS,0x00000001); - WriteReg_32(DBSC_D3_DBSCHRW1,0x00000046); - WriteReg_32(DBSC_D3_SCFCTST0,0x0D020C04); - WriteReg_32(DBSC_D3_SCFCTST1,0x0305040C); - - WriteReg_32(DBSC_D3_DBPDLK0,0x0000A55A); - WriteReg_32(DBSC_D3_DBCMD,0x01000001); - WriteReg_32(DBSC_D3_DBCMD,0x08000000); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); - WriteReg_32(DBSC_D3_DBPDRGD0,0x80010000); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); - while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000008); - WriteReg_32(DBSC_D3_DBPDRGD0,0x000B8000); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090); - WriteReg_32(DBSC_D3_DBPDRGD0,0x04058904); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000091); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000095); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BBAD); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000099); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0007BB6B); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090); - WriteReg_32(DBSC_D3_DBPDRGD0,0x04058900); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0024641E); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); - WriteReg_32(DBSC_D3_DBPDRGD0,0x00010073); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); - while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0C058900); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000090); - WriteReg_32(DBSC_D3_DBPDRGD0,0x04058900); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); - while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0780C700); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007); - while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000004); - WriteReg_32(DBSC_D3_DBPDRGD0,0x08C05FF0); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000022); - WriteReg_32(DBSC_D3_DBPDRGD0,0x1000040B); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000023); - WriteReg_32(DBSC_D3_DBPDRGD0,0x2D9C0B66); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000024); - WriteReg_32(DBSC_D3_DBPDRGD0,0x2A88C400); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000025); - WriteReg_32(DBSC_D3_DBPDRGD0,0x30005200); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000026); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0014A9C9); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000027); - WriteReg_32(DBSC_D3_DBPDRGD0,0x00000D70); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000028); - WriteReg_32(DBSC_D3_DBPDRGD0,0x00000046); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000029); - WriteReg_32(DBSC_D3_DBPDRGD0,0x00000098); - WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C); - WriteReg_32(DBSC_D3_DBPDRGD0,0x81003047); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000020); - WriteReg_32(DBSC_D3_DBPDRGD0,0x00181884); - WriteReg_32(DBSC_D3_DBPDRGA0,0x0000001A); - WriteReg_32(DBSC_D3_DBPDRGD0,0x33C03C10); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); - while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A7); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A8); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A9); - WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C7); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C8); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0D0D0D0D); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C9); - WriteReg_32(DBSC_D3_DBPDRGD0,0x000D0D0D); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x0000000E); - RegVal_R2 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8) >> 0x1; - RegVal_R3 = (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2; - RegVal_R6 = (RegVal_R2 << 24) + (RegVal_R2 << 16) + (RegVal_R2 << 8) + RegVal_R2; - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000011); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000012); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R3); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000016); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000017); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000018); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000019); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R6); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); - WriteReg_32(DBSC_D3_DBPDRGD0,0x00010181); - WriteReg_32(DBSC_D3_DBCMD,0x08000001); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); - while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); - WriteReg_32(DBSC_D3_DBPDRGD0,0x00010601); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); - while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - for (uint32_t i = 0; i<2; i++) - { - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20); - RegVal_R5 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8; - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20); - RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20); - RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007); - if ( RegVal_R6 > 0 ) - { - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R6); - } else - { - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | RegVal_R7); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF)); - } - } - - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005); - WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00C0); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0); - WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0); - WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); - WriteReg_32(DBSC_D3_DBPDRGD0,0x00010801); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); - while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000005); - WriteReg_32(DBSC_D3_DBPDRGD0,0xC1AA00D8); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0001F001); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); - while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000AF); - RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0); - WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00))); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000CF); - RegVal_R2 = ReadReg_32(DBSC_D3_DBPDRGD0); - WriteReg_32(DBSC_D3_DBPDRGD0,(((RegVal_R2 + 0x1) & 0x000000FF) | (RegVal_R2 & 0xFFFFFF00))); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0); - WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0); - WriteReg_32(DBSC_D3_DBPDRGD0,0x7C000285); - WriteReg_32(DBSC_D3_DBPDRGA0,0x0000002C); - WriteReg_32(DBSC_D3_DBPDRGD0,0x81003087); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); - WriteReg_32(DBSC_D3_DBPDRGD0,0x00010401); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); - while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - for (uint32_t i = 0; i < 2; i++) - { - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B1 + i*0x20); - RegVal_R5 = ((ReadReg_32(DBSC_D3_DBPDRGD0) & 0x0000FF00) >> 0x8); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B4 + i*0x20); - RegVal_R6 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x000000FF); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B3 + i*0x20); - RegVal_R7 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0x00000007); - RegVal_R12 = (RegVal_R5 >> 0x2); - if ( RegVal_R12 < RegVal_R6 ) - { - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF)); - } - else - { - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B2 + i*0x20); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007)); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_D3_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000B0 + i*0x20); - WriteReg_32(DBSC_D3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF)); - } - } - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000A0); - WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5); - WriteReg_32(DBSC_D3_DBPDRGA0,0x000000C0); - WriteReg_32(DBSC_D3_DBPDRGD0,0x7C0002C5); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000001); - WriteReg_32(DBSC_D3_DBPDRGD0,0x00015001); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000006); - while ( (BIT0 & ReadReg_32(DBSC_D3_DBPDRGD0)) == 0 ); - - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000003); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0380C700); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000007); - while ( (BIT30 & ReadReg_32(DBSC_D3_DBPDRGD0)) != 0 ); - WriteReg_32(DBSC_D3_DBPDRGA0,0x00000021); - WriteReg_32(DBSC_D3_DBPDRGD0,0x0024643E); - - WriteReg_32(DBSC_D3_DBBUS0CNF1,0x00000010); - WriteReg_32(DBSC_D3_DBCALCNF,0x0100401B); - WriteReg_32(DBSC_D3_DBRFCNF1,0x00080C30); - WriteReg_32(DBSC_D3_DBRFCNF2,0x00010000); - WriteReg_32(DBSC_D3_DBDFICUPDCNF,0x40100001); - WriteReg_32(DBSC_D3_DBRFEN,0x00000001); - WriteReg_32(DBSC_D3_DBACEN,0x00000001); - WriteReg_32(DBSC_D3_DBPDLK0,0x00000000); - WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000); + uint32_t i, r2, r3, r5, r6, r7, r12; + + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + mmio_write_32(DBSC_DBKIND, 0x00000007); + mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a01); + mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); + mmio_write_32(DBSC_DBTR0, 0x0000000B); + mmio_write_32(DBSC_DBTR1, 0x00000008); + mmio_write_32(DBSC_DBTR2, 0x00000000); + mmio_write_32(DBSC_DBTR3, 0x0000000B); + mmio_write_32(DBSC_DBTR4, 0x000B000B); + mmio_write_32(DBSC_DBTR5, 0x00000027); + mmio_write_32(DBSC_DBTR6, 0x0000001C); + mmio_write_32(DBSC_DBTR7, 0x00060006); + mmio_write_32(DBSC_DBTR8, 0x00000020); + mmio_write_32(DBSC_DBTR9, 0x00000006); + mmio_write_32(DBSC_DBTR10, 0x0000000C); + mmio_write_32(DBSC_DBTR11, 0x0000000A); + mmio_write_32(DBSC_DBTR12, 0x00120012); + mmio_write_32(DBSC_DBTR13, 0x000000D0); + mmio_write_32(DBSC_DBTR14, 0x00140005); + mmio_write_32(DBSC_DBTR15, 0x00050004); + mmio_write_32(DBSC_DBTR16, 0x071F0305); + mmio_write_32(DBSC_DBTR17, 0x040C0000); + mmio_write_32(DBSC_DBTR18, 0x00000200); + mmio_write_32(DBSC_DBTR19, 0x01000040); + mmio_write_32(DBSC_DBTR20, 0x020000D8); + mmio_write_32(DBSC_DBTR21, 0x00040004); + mmio_write_32(DBSC_DBBL, 0x00000000); + mmio_write_32(DBSC_DBODT0, 0x00000001); + mmio_write_32(DBSC_DBADJ0, 0x00000001); + mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); + mmio_write_32(DBSC_DBDFICNT0, 0x00000010); + mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); + mmio_write_32(DBSC_DBSCHRW1, 0x00000046); + mmio_write_32(DBSC_SCFCTST0, 0x0D020C04); + mmio_write_32(DBSC_SCFCTST1, 0x0305040C); + + mmio_write_32(DBSC_DBPDLK0, 0x0000A55A); + mmio_write_32(DBSC_DBCMD, 0x01000001); + mmio_write_32(DBSC_DBCMD, 0x08000000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x80010000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000008); + mmio_write_32(DBSC_DBPDRGD0, 0x000B8000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD0, 0x04058904); + mmio_write_32(DBSC_DBPDRGA0, 0x00000091); + mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA0, 0x00000095); + mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD); + mmio_write_32(DBSC_DBPDRGA0, 0x00000099); + mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD0, 0x04058900); + mmio_write_32(DBSC_DBPDRGA0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD0, 0x0024641E); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010073); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD0, 0x0C058900); + mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD0, 0x04058900); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD0, 0x0780C700); + mmio_write_32(DBSC_DBPDRGA0, 0x00000007); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000004); + mmio_write_32(DBSC_DBPDRGD0, 0x08C05FF0); + mmio_write_32(DBSC_DBPDRGA0, 0x00000022); + mmio_write_32(DBSC_DBPDRGD0, 0x1000040B); + mmio_write_32(DBSC_DBPDRGA0, 0x00000023); + mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66); + mmio_write_32(DBSC_DBPDRGA0, 0x00000024); + mmio_write_32(DBSC_DBPDRGD0, 0x2A88C400); + mmio_write_32(DBSC_DBPDRGA0, 0x00000025); + mmio_write_32(DBSC_DBPDRGD0, 0x30005200); + mmio_write_32(DBSC_DBPDRGA0, 0x00000026); + mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9); + mmio_write_32(DBSC_DBPDRGA0, 0x00000027); + mmio_write_32(DBSC_DBPDRGD0, 0x00000D70); + mmio_write_32(DBSC_DBPDRGA0, 0x00000028); + mmio_write_32(DBSC_DBPDRGD0, 0x00000046); + mmio_write_32(DBSC_DBPDRGA0, 0x00000029); + mmio_write_32(DBSC_DBPDRGD0, 0x00000098); + mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD0, 0x81003047); + mmio_write_32(DBSC_DBPDRGA0, 0x00000020); + mmio_write_32(DBSC_DBPDRGD0, 0x00181884); + mmio_write_32(DBSC_DBPDRGA0, 0x0000001A); + mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x000000A7); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000A8); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000A9); + mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C7); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C8); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C9); + mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); + + mmio_write_32(DBSC_DBPDRGA0, 0x0000000E); + r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0x0000FF00) >> 0x9; + r3 = (r2 << 16) + (r2 << 8) + r2; + r6 = (r2 << 24) + (r2 << 16) + (r2 << 8) + r2; + mmio_write_32(DBSC_DBPDRGA0, 0x00000011); + mmio_write_32(DBSC_DBPDRGD0, r3); + mmio_write_32(DBSC_DBPDRGA0, 0x00000012); + mmio_write_32(DBSC_DBPDRGD0, r3); + mmio_write_32(DBSC_DBPDRGA0, 0x00000016); + mmio_write_32(DBSC_DBPDRGD0, r6); + mmio_write_32(DBSC_DBPDRGA0, 0x00000017); + mmio_write_32(DBSC_DBPDRGD0, r6); + mmio_write_32(DBSC_DBPDRGA0, 0x00000018); + mmio_write_32(DBSC_DBPDRGD0, r6); + mmio_write_32(DBSC_DBPDRGA0, 0x00000019); + mmio_write_32(DBSC_DBPDRGD0, r6); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010181); + mmio_write_32(DBSC_DBCMD, 0x08000001); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010601); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + for (i = 0; i < 2; i++) { + mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8; + mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + if (r6 > 0) { + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; + + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | r6); + } else { + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | r7); + + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | + ((r6 + (r5 << 1)) & 0xFF)); + } + } + + mmio_write_32(DBSC_DBPDRGA0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0); + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010801); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x0001F001); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x000000AF); + r2 = mmio_read_32(DBSC_DBPDRGD0); + mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); + mmio_write_32(DBSC_DBPDRGA0, 0x000000CF); + r2 = mmio_read_32(DBSC_DBPDRGD0); + mmio_write_32(DBSC_DBPDRGD0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00)); + + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD0, 0x81003087); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010401); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + for (i = 0; i < 2; i++) { + mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8; + mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; + + mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + r12 = (r5 >> 0x2); + + if (r12 < r6) { + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; + + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; + + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF)); + } else { + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7)); + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | + ((r6 + r5 + + (r5 >> 1) + r12) & 0xFF)); + } + } + + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00015001); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD0, 0x0380C700); + mmio_write_32(DBSC_DBPDRGA0, 0x00000007); + while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30)) + ; + mmio_write_32(DBSC_DBPDRGA0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD0, 0x0024643E); + + mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); + mmio_write_32(DBSC_DBCALCNF, 0x0100401B); + mmio_write_32(DBSC_DBRFCNF1, 0x00080C30); + mmio_write_32(DBSC_DBRFCNF2, 0x00010000); + mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); + mmio_write_32(DBSC_DBRFEN, 0x00000001); + mmio_write_32(DBSC_DBACEN, 0x00000001); + mmio_write_32(DBSC_DBPDLK0, 0x00000000); + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); #ifdef ddr_qos_init_setting // only for non qos_init - WriteReg_32(DBSC_D3_DBSYSCNT0,0x00001234); - WriteReg_32(DBSC_D3_DBCAM0CNF1,0x00043218); - WriteReg_32(DBSC_D3_DBCAM0CNF2,0x000000F4); - WriteReg_32(DBSC_D3_DBSCHCNT0,0x000f0037); - WriteReg_32(DBSC_D3_DBSCHSZ0,0x00000001); - WriteReg_32(DBSC_D3_DBSCHRW0,0x22421111); - WriteReg_32(DBSC_D3_SCFCTST2,0x012F1123); - WriteReg_32(DBSC_D3_DBSCHQOS00,0x00000F00); - WriteReg_32(DBSC_D3_DBSCHQOS01,0x00000B00); - WriteReg_32(DBSC_D3_DBSCHQOS02,0x00000000); - WriteReg_32(DBSC_D3_DBSCHQOS03,0x00000000); - WriteReg_32(DBSC_D3_DBSCHQOS40,0x00000300); - WriteReg_32(DBSC_D3_DBSCHQOS41,0x000002F0); - WriteReg_32(DBSC_D3_DBSCHQOS42,0x00000200); - WriteReg_32(DBSC_D3_DBSCHQOS43,0x00000100); - WriteReg_32(DBSC_D3_DBSCHQOS90,0x00000300); - WriteReg_32(DBSC_D3_DBSCHQOS91,0x000002F0); - WriteReg_32(DBSC_D3_DBSCHQOS92,0x00000200); - WriteReg_32(DBSC_D3_DBSCHQOS93,0x00000100); - WriteReg_32(DBSC_D3_DBSCHQOS130,0x00000100); - WriteReg_32(DBSC_D3_DBSCHQOS131,0x000000F0); - WriteReg_32(DBSC_D3_DBSCHQOS132,0x000000A0); - WriteReg_32(DBSC_D3_DBSCHQOS133,0x00000040); - WriteReg_32(DBSC_D3_DBSCHQOS140,0x000000C0); - WriteReg_32(DBSC_D3_DBSCHQOS141,0x000000B0); - WriteReg_32(DBSC_D3_DBSCHQOS142,0x00000080); - WriteReg_32(DBSC_D3_DBSCHQOS143,0x00000040); - WriteReg_32(DBSC_D3_DBSCHQOS150,0x00000040); - WriteReg_32(DBSC_D3_DBSCHQOS151,0x00000030); - WriteReg_32(DBSC_D3_DBSCHQOS152,0x00000020); - WriteReg_32(DBSC_D3_DBSCHQOS153,0x00000010); - WriteReg_32(0xE67F0018,0x00000001); - WriteReg_32(DBSC_D3_DBSYSCNT0,0x00000000); + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); + mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4); + mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037); + mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); + mmio_write_32(DBSC_DBSCHRW0, 0x22421111); + mmio_write_32(DBSC_SCFCTST2, 0x012F1123); + mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00); + mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00); + mmio_write_32(DBSC_DBSCHQOS02, 0x00000000); + mmio_write_32(DBSC_DBSCHQOS03, 0x00000000); + mmio_write_32(DBSC_DBSCHQOS40, 0x00000300); + mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0); + mmio_write_32(DBSC_DBSCHQOS42, 0x00000200); + mmio_write_32(DBSC_DBSCHQOS43, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS90, 0x00000300); + mmio_write_32(DBSC_DBSCHQOS91, 0x000002F0); + mmio_write_32(DBSC_DBSCHQOS92, 0x00000200); + mmio_write_32(DBSC_DBSCHQOS93, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS130, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0); + mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0); + mmio_write_32(DBSC_DBSCHQOS133, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0); + mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0); + mmio_write_32(DBSC_DBSCHQOS142, 0x00000080); + mmio_write_32(DBSC_DBSCHQOS143, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS150, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS151, 0x00000030); + mmio_write_32(DBSC_DBSCHQOS152, 0x00000020); + mmio_write_32(DBSC_DBSCHQOS153, 0x00000010); + mmio_write_32(0xE67F0018, 0x00000001); + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); #endif } -#define PRR (0xFFF00044U) -#define PRR_PRODUCT_MASK (0x00007F00U) -#define PRR_PRODUCT_D3 (0x00005800U) +#define PRR 0xFFF00044U +#define PRR_PRODUCT_MASK 0x00007F00U +#define PRR_PRODUCT_D3 0x00005800U -#define RST_MODEMR (0xE6160060) -#define MODEMR_MD19 (0x00080000U) +#define MODEMR_MD19 BIT(19) int32_t rcar_dram_init(void) { @@ -669,15 +678,14 @@ int32_t rcar_dram_init(void) uint32_t ddr_mbps; reg = mmio_read_32(PRR); - - if (PRR_PRODUCT_D3 != (reg & PRR_PRODUCT_MASK)) { + if ((reg & PRR_PRODUCT_MASK) != PRR_PRODUCT_D3) { ERROR("LSI Product ID (PRR=0x%x) DDR initialize not supported.\n", reg); panic(); } reg = mmio_read_32(RST_MODEMR); - if (MODEMR_MD19 == (reg & MODEMR_MD19)) { + if (reg & MODEMR_MD19) { init_ddr_d3_1866(); ddr_mbps = 1866; } else { diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c index 544cadc83f..7aedc88d6b 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c @@ -1,1695 +1,1711 @@ /* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include <lib/mmio.h> #include <stdint.h> #include <common/debug.h> -#include "boot_init_dram_regdef_e3.h" -#include "ddr_init_e3.h" +#include "boot_init_dram.h" +#include "boot_init_dram_regdef.h" #include "../dram_sub_func.h" -/* rev.0.04 add variables */ -/******************************************************************************* - * variables - ******************************************************************************/ -uint32_t ddrBackup; - -/* rev.0.03 add Prototypes */ -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/* static uint32_t init_ddr(void); rev.0.04 */ -/* static uint32_t recovery_from_backup_mode(void); rev.0.04 */ -/* int32_t dram_update_boot_status(uint32_t status); rev.0.04 */ - -/* rev.0.03 add Comment */ -/******************************************************************************* - * register write/read function - ******************************************************************************/ -static void WriteReg_32(uint32_t a, uint32_t v) -{ - (*(volatile uint32_t*)(uintptr_t)a) = v; -} /* WriteReg_32 */ +#define RCAR_E3_DDR_VERSION "rev.0.12" -static uint32_t ReadReg_32(uint32_t a) -{ - uint32_t w = (*(volatile uint32_t*)(uintptr_t)a); - return w; -} /* ReadReg_32 */ +/* Average periodic refresh interval[ns]. Support 3900,7800 */ +#ifdef ddr_qos_init_setting +#define REFRESH_RATE 3900U +#else +#if RCAR_REF_INT == 1 +#define REFRESH_RATE 7800U +#else +#define REFRESH_RATE 3900U +#endif +#endif -/* rev.0.04 add Comment */ -/******************************************************************************* +/* * Initialize ddr - ******************************************************************************/ + */ uint32_t init_ddr(void) { - uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i; - uint32_t ddr_md; - -/* rev.0.08 */ - uint32_t RegVal, j; - uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16; - uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4]; - uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2; -/* rev.0.10 */ - uint32_t pdr_ctl; -/* rev.0.11 */ - uint32_t byp_ctl; - -/* rev.0.08 */ - if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) { - pdqsr_ctl = 1; - lcdl_ctl = 1; - pdr_ctl = 1; /* rev.0.10 */ - byp_ctl = 1; /* rev.0.11 */ - } else { - pdqsr_ctl = 0; - lcdl_ctl = 0; - pdr_ctl = 0; /* rev.0.10 */ - byp_ctl = 0; /* rev.0.11 */ - } - - /* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */ - ddr_md = (ReadReg_32(RST_MODEMR) >> 19) & BIT0; - - /* 1584Mbps setting */ - if (ddr_md == 0) { - /* CPG setting ===============================================*/ - WriteReg_32(CPG_CPGWPR, 0x5A5AFFFF); - WriteReg_32(CPG_CPGWPCR, 0xA5A50000); - - WriteReg_32(CPG_SRCR4, 0x20000000); - - WriteReg_32(0xE61500DC, 0xe2200000); /* Change to 1584Mbps */ - while ((BIT11 & ReadReg_32(CPG_PLLECR)) == 0); - - WriteReg_32(CPG_SRSTCLR4, 0x20000000); - - WriteReg_32(CPG_CPGWPCR, 0xA5A50001); - - /* CPG setting ===============================================*/ - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234); - WriteReg_32(DBSC_E3_DBKIND, 0x00000007); + uint32_t i, r2, r5, r6, r7, r12; + uint32_t ddr_md; + uint32_t regval, j; + uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4; + uint32_t bdlcount_0c_div8, bdlcount_0c_div16; + uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4]; + uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2; + uint32_t pdr_ctl; + uint32_t byp_ctl; + + if ((mmio_read_32(0xFFF00044) & 0x000000FF) == 0x00000000) { + pdqsr_ctl = 1; + lcdl_ctl = 1; + pdr_ctl = 1; + byp_ctl = 1; + } else { + pdqsr_ctl = 0; + lcdl_ctl = 0; + pdr_ctl = 0; + byp_ctl = 0; + } + + /* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */ + ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & BIT(0); + + /* 1584Mbps setting */ + if (ddr_md == 0) { + mmio_write_32(CPG_CPGWPR, 0x5A5AFFFF); + mmio_write_32(CPG_CPGWPCR, 0xA5A50000); + + mmio_write_32(CPG_SRCR4, 0x20000000); + + mmio_write_32(0xE61500DC, 0xe2200000); /* Change to 1584Mbps */ + while (!(mmio_read_32(CPG_PLLECR) & BIT(11))) + ; + + mmio_write_32(CPG_SRSTCLR4, 0x20000000); + + mmio_write_32(CPG_CPGWPCR, 0xA5A50001); + } + + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + mmio_write_32(DBSC_DBKIND, 0x00000007); #if RCAR_DRAM_DDR3L_MEMCONF == 0 - WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02); /* 1GB */ + mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a02); /* 1GB */ #else - WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /* 2GB(default) */ + mmio_write_32(DBSC_DBMEMCONF00, 0x10030a02); /* 2GB(default) */ #endif #if RCAR_DRAM_DDR3L_MEMDUAL == 1 - RegVal_R2 = (ReadReg_32(0xE6790614)); - WriteReg_32(0xE6790614, RegVal_R2 | 0x00000003); /* MCS1_N/MODT1 are activated. */ + r2 = mmio_read_32(0xE6790614); + mmio_write_32(0xE6790614, r2 | 0x3); /* MCS1_N/MODT1 are activated. */ #endif - - WriteReg_32(DBSC_E3_DBPHYCONF0, 0x00000001); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBTR0, 0x0000000B); - WriteReg_32(DBSC_E3_DBTR1, 0x00000008); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBTR0, 0x0000000D); - WriteReg_32(DBSC_E3_DBTR1, 0x00000009); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBTR2, 0x00000000); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBTR3, 0x0000000B); - WriteReg_32(DBSC_E3_DBTR4, 0x000B000B); - WriteReg_32(DBSC_E3_DBTR5, 0x00000027); - WriteReg_32(DBSC_E3_DBTR6, 0x0000001C); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBTR3, 0x0000000D); - WriteReg_32(DBSC_E3_DBTR4, 0x000D000D); - WriteReg_32(DBSC_E3_DBTR5, 0x0000002D); - WriteReg_32(DBSC_E3_DBTR6, 0x00000020); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBTR7, 0x00060006); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBTR8, 0x00000020); - WriteReg_32(DBSC_E3_DBTR9, 0x00000006); - WriteReg_32(DBSC_E3_DBTR10, 0x0000000C); - WriteReg_32(DBSC_E3_DBTR11, 0x0000000A); - WriteReg_32(DBSC_E3_DBTR12, 0x00120012); - WriteReg_32(DBSC_E3_DBTR13, 0x000000CE); - WriteReg_32(DBSC_E3_DBTR14, 0x00140005); - WriteReg_32(DBSC_E3_DBTR15, 0x00050004); - WriteReg_32(DBSC_E3_DBTR16, 0x071F0305); - WriteReg_32(DBSC_E3_DBTR17, 0x040C0000); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBTR8, 0x00000021); - WriteReg_32(DBSC_E3_DBTR9, 0x00000007); - WriteReg_32(DBSC_E3_DBTR10, 0x0000000E); - WriteReg_32(DBSC_E3_DBTR11, 0x0000000C); - WriteReg_32(DBSC_E3_DBTR12, 0x00140014); - WriteReg_32(DBSC_E3_DBTR13, 0x000000F2); - WriteReg_32(DBSC_E3_DBTR14, 0x00170006); - WriteReg_32(DBSC_E3_DBTR15, 0x00060005); - WriteReg_32(DBSC_E3_DBTR16, 0x09210507); - WriteReg_32(DBSC_E3_DBTR17, 0x040E0000); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBTR18, 0x00000200); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBTR19, 0x01000040); - WriteReg_32(DBSC_E3_DBTR20, 0x020000D6); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBTR19, 0x0129004B); - WriteReg_32(DBSC_E3_DBTR20, 0x020000FB); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBTR21, 0x00040004); - WriteReg_32(DBSC_E3_DBBL, 0x00000000); - WriteReg_32(DBSC_E3_DBODT0, 0x00000001); - WriteReg_32(DBSC_E3_DBADJ0, 0x00000001); - WriteReg_32(DBSC_E3_DBSYSCONF1, 0x00000002); - WriteReg_32(DBSC_E3_DBDFICNT0, 0x00000010); - WriteReg_32(DBSC_E3_DBBCAMDIS, 0x00000001); - WriteReg_32(DBSC_E3_DBSCHRW1, 0x00000046); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_SCFCTST0, 0x0D050B03); - WriteReg_32(DBSC_E3_SCFCTST1, 0x0306030C); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_SCFCTST0, 0x0C050B03); - WriteReg_32(DBSC_E3_SCFCTST1, 0x0305030C); - } /* ddr_md */ - - /* rev.0.03 add Comment */ - /**************************************************************************** - * Initial_Step0( INITBYP ) - ***************************************************************************/ - WriteReg_32(DBSC_E3_DBPDLK0, 0x0000A55A); - WriteReg_32(DBSC_E3_DBCMD, 0x01840001); - WriteReg_32(DBSC_E3_DBCMD, 0x08840000); - NOTICE("BL2: [COLD_BOOT]\n"); /* rev.0.11 */ - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x80010000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - /* rev.0.03 add Comment */ - /**************************************************************************** - * Initial_Step1( ZCAL,PLLINIT,DCAL,PHYRST training ) - ***************************************************************************/ - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000008); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x000B8000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058904); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A04); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000091); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000095); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BBAD); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000099); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024641E); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010073); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - /* rev.0.03 add Comment */ - /**************************************************************************** - * Initial_Step2( DRAMRST/DRAMINT training ) - ***************************************************************************/ - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003); - if (byp_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C720); - } else { - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C700); - } - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007); - while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000004); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 792 / 125) - 400 + 0x08B00000); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 928 / 125) - 400 + 0x0A300000); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000022); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x1000040B); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000023); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x2D9C0B66); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x35A00D77); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000024); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A88B400); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A8A2C28); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000025); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005200); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005E00); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000026); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014A9C9); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014CB49); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000027); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000D70); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000F14); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000028); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000046); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000029); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - if (REFRESH_RATE > 3900) { - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000018); /* [7]SRT=0 */ - } else { - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000098); /* [7]SRT=1 */ - } - } else { /* 1856Mbps */ - if (REFRESH_RATE > 3900) { - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000020); /* [7]SRT=0 */ - } else { - WriteReg_32(DBSC_E3_DBPDRGD0, 0x000000A0); /* [7]SRT=1 */ - } /* REFRESH_RATE */ - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003047); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000020); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00181884); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000001A); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x33C03C10); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A7); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A8); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A9); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C7); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C8); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C9); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E7); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E8); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E9); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000107); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000108); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000109); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010181); - WriteReg_32(DBSC_E3_DBCMD, 0x08840001); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - /* rev.0.03 add Comment */ - /**************************************************************************** - * Initial_Step3( WL/QSG training ) - ***************************************************************************/ - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010601); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - for (i = 0; i < 4; i++) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20); - RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8; - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20); - RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20); - RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007); - if (RegVal_R6 > 0) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); - RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R6); - } else { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); - RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R7); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF)); - } /* RegVal_R6 */ - } /* for i */ - - /* rev.0.10 move Comment */ - /**************************************************************************** - * Initial_Step4( WLADJ training ) - ***************************************************************************/ - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005); - WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00C0); - - /* rev.0.08 */ - if (pdqsr_ctl == 1){} else { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - } - - /* PDR always off */ /* rev.0.10 */ - if (pdr_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - } - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010801); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - /**************************************************************************** - * Initial_Step5(Read Data Bit Deskew) - ***************************************************************************/ - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005); - WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00D8); - - /* rev.0.08 */ - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00011001); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - -if (pdqsr_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); -} - - /* PDR dynamic */ /* rev.0.10 */ - if (pdr_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - } - - /**************************************************************************** - * Initial_Step6(Write Data Bit Deskew) - ***************************************************************************/ - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00012001); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - /**************************************************************************** - * Initial_Step7(Read Data Eye Training) - ***************************************************************************/ -if (pdqsr_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); -} - - /* PDR always off */ /* rev.0.10 */ - if (pdr_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - } - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00014001); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - -if (pdqsr_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); -} - - /* PDR dynamic */ /* rev.0.10 */ - if (pdr_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - } - - /**************************************************************************** - * Initial_Step8(Write Data Eye Training) - ***************************************************************************/ - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00018001); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - /* rev.0.03 add Comment */ - /**************************************************************************** - * Initial_Step3_2( DQS Gate Training ) - ***************************************************************************/ - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003087); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010401); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - for (i = 0; i < 4; i++) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20); - RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20); - RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20); - RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007); - RegVal_R12 = (RegVal_R5 >> 0x2); - if (RegVal_R12 < RegVal_R6) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); - RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF)); - } else { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); - RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | (RegVal_R7 & 0x00000007)); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF)); - } /* RegVal_R12 < RegVal_R6 */ - } /* for i */ - - /* rev.0.10 move Comment */ - /**************************************************************************** - * Initial_Step5-2_7-2( Rd bit Rd eye ) - ***************************************************************************/ -/* rev.0.08 */ - if (pdqsr_ctl == 1){} else { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - } - - /* PDR always off */ /* rev.0.10 */ - if (pdr_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - } - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00015001); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - -/* rev.0.08 */ - if (lcdl_ctl == 1) { - for (i = 0; i < 4; i++) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20); - bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8); - bdlcount_0c_div2 = (bdlcount_0c >> 1); - bdlcount_0c_div4 = (bdlcount_0c >> 2); - bdlcount_0c_div8 = (bdlcount_0c >> 3); - bdlcount_0c_div16 = (bdlcount_0c >> 4); - - if (ddr_md == 0) { /* 1584Mbps */ - lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8; - lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16; - } else { /* 1856Mbps */ - lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4; - lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4; - } /* ddr_md */ - - if (dqsgd_0c > lcdl_judge1) { - if (dqsgd_0c <= lcdl_judge2) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_E3_DBPDRGD0, ((dqsgd_0c - bdlcount_0c_div8) | RegVal)); - } else { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); - gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); - RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal | (gatesl_0c + 1))); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20); - RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0)); - rdqsd_0c = (RegVal & 0x0000FF00) >> 8; - rdqsnd_0c = (RegVal & 0x00FF0000) >> 16; - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20); - WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF) | ((rdqsd_0c + bdlcount_0c_div4) << 8) | ((rdqsnd_0c + bdlcount_0c_div4) << 16))); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20); - RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0)); - rbd_0c[0] = (RegVal) &0x0000001f; - rbd_0c[1] = (RegVal >> 8) & 0x0000001f; - rbd_0c[2] = (RegVal >> 16) & 0x0000001f; - rbd_0c[3] = (RegVal >> 24) & 0x0000001f; - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20); - RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0); - for (j = 0; j < 4; j++) { - rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); - if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; - RegVal = RegVal | (rbd_0c[j] << 8 * j); + mmio_write_32(DBSC_DBPHYCONF0, 0x1); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBTR0, 0xB); + mmio_write_32(DBSC_DBTR1, 0x8); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBTR0, 0xD); + mmio_write_32(DBSC_DBTR1, 0x9); + } + + mmio_write_32(DBSC_DBTR2, 0x00000000); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBTR3, 0x0000000B); + mmio_write_32(DBSC_DBTR4, 0x000B000B); + mmio_write_32(DBSC_DBTR5, 0x00000027); + mmio_write_32(DBSC_DBTR6, 0x0000001C); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBTR3, 0x0000000D); + mmio_write_32(DBSC_DBTR4, 0x000D000D); + mmio_write_32(DBSC_DBTR5, 0x0000002D); + mmio_write_32(DBSC_DBTR6, 0x00000020); + } + + mmio_write_32(DBSC_DBTR7, 0x00060006); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBTR8, 0x00000020); + mmio_write_32(DBSC_DBTR9, 0x00000006); + mmio_write_32(DBSC_DBTR10, 0x0000000C); + mmio_write_32(DBSC_DBTR11, 0x0000000A); + mmio_write_32(DBSC_DBTR12, 0x00120012); + mmio_write_32(DBSC_DBTR13, 0x000000CE); + mmio_write_32(DBSC_DBTR14, 0x00140005); + mmio_write_32(DBSC_DBTR15, 0x00050004); + mmio_write_32(DBSC_DBTR16, 0x071F0305); + mmio_write_32(DBSC_DBTR17, 0x040C0000); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBTR8, 0x00000021); + mmio_write_32(DBSC_DBTR9, 0x00000007); + mmio_write_32(DBSC_DBTR10, 0x0000000E); + mmio_write_32(DBSC_DBTR11, 0x0000000C); + mmio_write_32(DBSC_DBTR12, 0x00140014); + mmio_write_32(DBSC_DBTR13, 0x000000F2); + mmio_write_32(DBSC_DBTR14, 0x00170006); + mmio_write_32(DBSC_DBTR15, 0x00060005); + mmio_write_32(DBSC_DBTR16, 0x09210507); + mmio_write_32(DBSC_DBTR17, 0x040E0000); + } + + mmio_write_32(DBSC_DBTR18, 0x00000200); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBTR19, 0x01000040); + mmio_write_32(DBSC_DBTR20, 0x020000D6); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBTR19, 0x0129004B); + mmio_write_32(DBSC_DBTR20, 0x020000FB); + } + + mmio_write_32(DBSC_DBTR21, 0x00040004); + mmio_write_32(DBSC_DBBL, 0x00000000); + mmio_write_32(DBSC_DBODT0, 0x00000001); + mmio_write_32(DBSC_DBADJ0, 0x00000001); + mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); + mmio_write_32(DBSC_DBDFICNT0, 0x00000010); + mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); + mmio_write_32(DBSC_DBSCHRW1, 0x00000046); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_SCFCTST0, 0x0D050B03); + mmio_write_32(DBSC_SCFCTST1, 0x0306030C); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_SCFCTST0, 0x0C050B03); + mmio_write_32(DBSC_SCFCTST1, 0x0305030C); + } + + /* + * Initial_Step0( INITBYP ) + */ + mmio_write_32(DBSC_DBPDLK0, 0x0000A55A); + mmio_write_32(DBSC_DBCMD, 0x01840001); + mmio_write_32(DBSC_DBCMD, 0x08840000); + NOTICE("BL2: [COLD_BOOT]\n"); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x80010000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + /* + * Initial_Step1( ZCAL,PLLINIT,DCAL,PHYRST training ) + */ + mmio_write_32(DBSC_DBPDRGA0, 0x00000008); + mmio_write_32(DBSC_DBPDRGD0, 0x000B8000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x04058904); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x04058A04); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000091); + mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA0, 0x00000095); + mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD); + mmio_write_32(DBSC_DBPDRGA0, 0x00000099); + mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x04058900); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x04058A00); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD0, 0x0024641E); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010073); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + /* + * Initial_Step2( DRAMRST/DRAMINT training ) + */ + mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x0C058900); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x04058900); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x04058A00); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000003); + if (byp_ctl == 1) + mmio_write_32(DBSC_DBPDRGD0, 0x0780C720); + else + mmio_write_32(DBSC_DBPDRGD0, 0x0780C700); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000007); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000004); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 792 / 125) - + 400 + 0x08B00000); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 928 / 125) - + 400 + 0x0A300000); + } + + mmio_write_32(DBSC_DBPDRGA0, 0x00000022); + mmio_write_32(DBSC_DBPDRGD0, 0x1000040B); + mmio_write_32(DBSC_DBPDRGA0, 0x00000023); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x35A00D77); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000024); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x2A88B400); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x2A8A2C28); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000025); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x30005200); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x30005E00); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000026); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x0014CB49); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000027); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x00000D70); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x00000F14); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000028); + mmio_write_32(DBSC_DBPDRGD0, 0x00000046); + mmio_write_32(DBSC_DBPDRGA0, 0x00000029); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + if (REFRESH_RATE > 3900) /* [7]SRT=0 */ + mmio_write_32(DBSC_DBPDRGD0, 0x18); + else /* [7]SRT=1 */ + mmio_write_32(DBSC_DBPDRGD0, 0x98); + } else { /* 1856Mbps */ + if (REFRESH_RATE > 3900) /* [7]SRT=0 */ + mmio_write_32(DBSC_DBPDRGD0, 0x20); + else /* [7]SRT=1 */ + mmio_write_32(DBSC_DBPDRGD0, 0xA0); + } + + mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD0, 0x81003047); + mmio_write_32(DBSC_DBPDRGA0, 0x00000020); + mmio_write_32(DBSC_DBPDRGD0, 0x00181884); + mmio_write_32(DBSC_DBPDRGA0, 0x0000001A); + mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x000000A7); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000A8); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000A9); + mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C7); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C8); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C9); + mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E7); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E8); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E9); + mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x00000107); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x00000108); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x00000109); + mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010181); + mmio_write_32(DBSC_DBCMD, 0x08840001); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + /* + * Initial_Step3( WL/QSG training ) + */ + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010601); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + for (i = 0; i < 4; i++) { + mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8; + mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + + if (r6 > 0) { + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | r6); + } else { + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | r7); + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | + ((r6 + ((r5) << 1)) & + 0xFF)); + } + } + + /* + * Initial_Step4( WLADJ training ) + */ + mmio_write_32(DBSC_DBPDRGA0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0); + + if (pdqsr_ctl == 0) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + } + + /* PDR always off */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + } + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010801); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + /* + * Initial_Step5(Read Data Bit Deskew) + */ + mmio_write_32(DBSC_DBPDRGA0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00011001); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + if (pdqsr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + } + + /* PDR dynamic */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + } + + /* + * Initial_Step6(Write Data Bit Deskew) + */ + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00012001); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + /* + * Initial_Step7(Read Data Eye Training) + */ + if (pdqsr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + } + + /* PDR always off */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + } + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00014001); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + if (pdqsr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + } + + /* PDR dynamic */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + } + + /* + * Initial_Step8(Write Data Eye Training) + */ + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00018001); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + /* + * Initial_Step3_2( DQS Gate Training ) + */ + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD0, 0x81003087); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010401); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + for (i = 0; i < 4; i++) { + mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); + r5 = ((mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8); + mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + r12 = (r5 >> 0x2); + if (r12 < r6) { + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF)); + } else { + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7)); + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 + r5 + + (r5 >> 1) + r12) & 0xFF)); } - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20); - RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0)); - rbd_0c[0] = (RegVal) &0x0000001f; - rbd_0c[1] = (RegVal >> 8) & 0x0000001f; - rbd_0c[2] = (RegVal >> 16) & 0x0000001f; - rbd_0c[3] = (RegVal >> 24) & 0x0000001f; - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20); - RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0); - for (j = 0; j < 4; j++) { - rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); - if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; - RegVal = RegVal | (rbd_0c[j] << 8 * j); + } + + /* + * Initial_Step5-2_7-2( Rd bit Rd eye ) + */ + if (pdqsr_ctl == 0) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + } + + /* PDR always off */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + } + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00015001); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + if (lcdl_ctl == 1) { + for (i = 0; i < 4; i++) { + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + dqsgd_0c = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); + bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> + 8; + bdlcount_0c_div2 = bdlcount_0c >> 1; + bdlcount_0c_div4 = bdlcount_0c >> 2; + bdlcount_0c_div8 = bdlcount_0c >> 3; + bdlcount_0c_div16 = bdlcount_0c >> 4; + + if (ddr_md == 0) { /* 1584Mbps */ + lcdl_judge1 = bdlcount_0c_div2 + + bdlcount_0c_div4 + + bdlcount_0c_div8; + lcdl_judge2 = bdlcount_0c + + bdlcount_0c_div4 + + bdlcount_0c_div16; + } else { /* 1856Mbps */ + lcdl_judge1 = bdlcount_0c_div2 + + bdlcount_0c_div4; + lcdl_judge2 = bdlcount_0c + + bdlcount_0c_div4; + } + + if (dqsgd_0c <= lcdl_judge1) + continue; + + if (dqsgd_0c <= lcdl_judge2) { + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD0) & + 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGD0, + (dqsgd_0c - bdlcount_0c_div8) | + regval); + } else { + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD0) & + 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGD0, regval); + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + gatesl_0c = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD0) & + 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGD0, regval | + (gatesl_0c + 1)); + mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20); + regval = (mmio_read_32(DBSC_DBPDRGD0)); + rdqsd_0c = (regval & 0xFF00) >> 8; + rdqsnd_0c = (regval & 0xFF0000) >> 16; + mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, + (regval & 0xFF0000FF) | + ((rdqsd_0c + + bdlcount_0c_div4) << 8) | + ((rdqsnd_0c + + bdlcount_0c_div4) << 16)); + mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20); + regval = (mmio_read_32(DBSC_DBPDRGD0)); + rbd_0c[0] = (regval) & 0x1f; + rbd_0c[1] = (regval >> 8) & 0x1f; + rbd_0c[2] = (regval >> 16) & 0x1f; + rbd_0c[3] = (regval >> 24) & 0x1f; + mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD0) & + 0xE0E0E0E0; + for (j = 0; j < 4; j++) { + rbd_0c[j] = rbd_0c[j] + + bdlcount_0c_div4; + if (rbd_0c[j] > 0x1F) + rbd_0c[j] = 0x1F; + regval = regval | (rbd_0c[j] << 8 * j); + } + mmio_write_32(DBSC_DBPDRGD0, regval); + mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20); + regval = (mmio_read_32(DBSC_DBPDRGD0)); + rbd_0c[0] = (regval) & 0x1f; + rbd_0c[1] = (regval >> 8) & 0x1f; + rbd_0c[2] = (regval >> 16) & 0x1f; + rbd_0c[3] = (regval >> 24) & 0x1f; + mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD0) & + 0xE0E0E0E0; + for (j = 0; j < 4; j++) { + rbd_0c[j] = rbd_0c[j] + + bdlcount_0c_div4; + if (rbd_0c[j] > 0x1F) + rbd_0c[j] = 0x1F; + regval = regval | (rbd_0c[j] << 8 * j); + } + mmio_write_32(DBSC_DBPDRGD0, regval); + } } - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); - } - } - } - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000002); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x07D81E37); - } - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003); - if (byp_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C720); - } else { - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C700); - } - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007); - while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024643E); - - WriteReg_32(DBSC_E3_DBBUS0CNF1, 0x00000010); - WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000 / REFRESH_RATE) + 0x01000000); - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 99 / 125) + 0x00080000); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 116 / 125) + 0x00080000); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBRFCNF2, 0x00010000); - WriteReg_32(DBSC_E3_DBDFICUPDCNF, 0x40100001); - WriteReg_32(DBSC_E3_DBRFEN, 0x00000001); - WriteReg_32(DBSC_E3_DBACEN, 0x00000001); - -/* rev.0.08 */ - if (pdqsr_ctl == 1) { - WriteReg_32(0xE67F0018, 0x00000001); - RegVal = ReadReg_32(0x40000000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000000); - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - } - - /* PDR dynamic */ /* rev.0.10 */ - if (pdr_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - } - - /* rev.0.03 add Comment */ - /**************************************************************************** - * Initial_Step9( Initial End ) - ***************************************************************************/ - WriteReg_32(DBSC_E3_DBPDLK0, 0x00000000); - WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000); - -#ifdef ddr_qos_init_setting /* only for non qos_init */ - WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234); - WriteReg_32(DBSC_E3_DBCAM0CNF1, 0x00043218); - WriteReg_32(DBSC_E3_DBCAM0CNF2, 0x000000F4); - WriteReg_32(DBSC_E3_DBSCHCNT0, 0x000f0037); - WriteReg_32(DBSC_E3_DBSCHSZ0, 0x00000001); - WriteReg_32(DBSC_E3_DBSCHRW0, 0x22421111); - WriteReg_32(DBSC_E3_SCFCTST2, 0x012F1123); - WriteReg_32(DBSC_E3_DBSCHQOS00, 0x00000F00); - WriteReg_32(DBSC_E3_DBSCHQOS01, 0x00000B00); - WriteReg_32(DBSC_E3_DBSCHQOS02, 0x00000000); - WriteReg_32(DBSC_E3_DBSCHQOS03, 0x00000000); - WriteReg_32(DBSC_E3_DBSCHQOS40, 0x00000300); - WriteReg_32(DBSC_E3_DBSCHQOS41, 0x000002F0); - WriteReg_32(DBSC_E3_DBSCHQOS42, 0x00000200); - WriteReg_32(DBSC_E3_DBSCHQOS43, 0x00000100); - WriteReg_32(DBSC_E3_DBSCHQOS90, 0x00000100); - WriteReg_32(DBSC_E3_DBSCHQOS91, 0x000000F0); - WriteReg_32(DBSC_E3_DBSCHQOS92, 0x000000A0); - WriteReg_32(DBSC_E3_DBSCHQOS93, 0x00000040); - WriteReg_32(DBSC_E3_DBSCHQOS130, 0x00000100); - WriteReg_32(DBSC_E3_DBSCHQOS131, 0x000000F0); - WriteReg_32(DBSC_E3_DBSCHQOS132, 0x000000A0); - WriteReg_32(DBSC_E3_DBSCHQOS133, 0x00000040); - WriteReg_32(DBSC_E3_DBSCHQOS140, 0x000000C0); - WriteReg_32(DBSC_E3_DBSCHQOS141, 0x000000B0); - WriteReg_32(DBSC_E3_DBSCHQOS142, 0x00000080); - WriteReg_32(DBSC_E3_DBSCHQOS143, 0x00000040); - WriteReg_32(DBSC_E3_DBSCHQOS150, 0x00000040); - WriteReg_32(DBSC_E3_DBSCHQOS151, 0x00000030); - WriteReg_32(DBSC_E3_DBSCHQOS152, 0x00000020); - WriteReg_32(DBSC_E3_DBSCHQOS153, 0x00000010); - -/* rev.0.08 */ - if (pdqsr_ctl == 1){} else { - WriteReg_32(0xE67F0018, 0x00000001); - } - - WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA0, 0x2); + mmio_write_32(DBSC_DBPDRGD0, 0x7D81E37); + } + + mmio_write_32(DBSC_DBPDRGA0, 0x00000003); + if (byp_ctl == 1) + mmio_write_32(DBSC_DBPDRGD0, 0x0380C720); + else + mmio_write_32(DBSC_DBPDRGD0, 0x0380C700); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000007); + while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30)) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD0, 0x0024643E); + + mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); + mmio_write_32(DBSC_DBCALCNF, (64000000 / REFRESH_RATE) + 0x01000000); + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBRFCNF1, + (REFRESH_RATE * 99 / 125) + 0x00080000); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBRFCNF1, + (REFRESH_RATE * 116 / 125) + 0x00080000); + } + + mmio_write_32(DBSC_DBRFCNF2, 0x00010000); + mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); + mmio_write_32(DBSC_DBRFEN, 0x00000001); + mmio_write_32(DBSC_DBACEN, 0x00000001); + + if (pdqsr_ctl == 1) { + mmio_write_32(0xE67F0018, 0x00000001); + regval = mmio_read_32(0x40000000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000000); + mmio_write_32(DBSC_DBPDRGD0, regval); + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + } + + /* PDR dynamic */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + } + + /* + * Initial_Step9( Initial End ) + */ + mmio_write_32(DBSC_DBPDLK0, 0x00000000); + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); + +#ifdef ddr_qos_init_setting /* only for non qos_init */ + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); + mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4); + mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037); + mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); + mmio_write_32(DBSC_DBSCHRW0, 0x22421111); + mmio_write_32(DBSC_SCFCTST2, 0x012F1123); + mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00); + mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00); + mmio_write_32(DBSC_DBSCHQOS02, 0x00000000); + mmio_write_32(DBSC_DBSCHQOS03, 0x00000000); + mmio_write_32(DBSC_DBSCHQOS40, 0x00000300); + mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0); + mmio_write_32(DBSC_DBSCHQOS42, 0x00000200); + mmio_write_32(DBSC_DBSCHQOS43, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS90, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0); + mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0); + mmio_write_32(DBSC_DBSCHQOS93, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS130, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0); + mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0); + mmio_write_32(DBSC_DBSCHQOS133, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0); + mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0); + mmio_write_32(DBSC_DBSCHQOS142, 0x00000080); + mmio_write_32(DBSC_DBSCHQOS143, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS150, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS151, 0x00000030); + mmio_write_32(DBSC_DBSCHQOS152, 0x00000020); + mmio_write_32(DBSC_DBSCHQOS153, 0x00000010); + + if (pdqsr_ctl == 0) + mmio_write_32(0xE67F0018, 0x00000001); + + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); #endif - return 1; /* rev.0.04 Restore the return code */ - -} /* init_ddr */ + return 1; +} -/* rev.0.04 add function */ -uint32_t recovery_from_backup_mode(void) +static uint32_t recovery_from_backup_mode(uint32_t ddr_backup) { - /**************************************************************************** - * recovery_Step0(DBSC Setting 1) / same "init_ddr" - ***************************************************************************/ - uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i; - uint32_t ddr_md; - uint32_t err; - -/* rev.0.08 */ - uint32_t RegVal, j; - uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16; - uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4]; - uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2; - /* rev.0.10 */ - uint32_t pdr_ctl; - /* rev.0.11 */ - uint32_t byp_ctl; - -/* rev.0.08 */ - if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) { - pdqsr_ctl = 1; - lcdl_ctl = 1; - pdr_ctl = 1; /* rev.0.10 */ - byp_ctl = 1; /* rev.0.11 */ - } else { - pdqsr_ctl = 0; - lcdl_ctl = 0; - pdr_ctl = 0; /* rev.0.10 */ - byp_ctl = 0; /* rev.0.11 */ - } - - /* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */ - ddr_md = (ReadReg_32(RST_MODEMR) >> 19) & BIT0; - - /* 1584Mbps setting */ - if (ddr_md == 0) { - /* CPG setting ===============================================*/ - WriteReg_32(CPG_CPGWPR, 0x5A5AFFFF); - WriteReg_32(CPG_CPGWPCR, 0xA5A50000); - - WriteReg_32(CPG_SRCR4, 0x20000000); - - WriteReg_32(0xE61500DC, 0xe2200000); /* Change to 1584Mbps */ - while ((BIT11 & ReadReg_32(CPG_PLLECR)) == 0); - - WriteReg_32(CPG_SRSTCLR4, 0x20000000); - - WriteReg_32(CPG_CPGWPCR, 0xA5A50001); - - /* CPG setting ===============================================*/ - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234); - WriteReg_32(DBSC_E3_DBKIND, 0x00000007); + /* + * recovery_Step0(DBSC Setting 1) / same "init_ddr" + */ + uint32_t r2, r5, r6, r7, r12, i; + uint32_t ddr_md; + uint32_t err; + uint32_t regval, j; + uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4; + uint32_t bdlcount_0c_div8, bdlcount_0c_div16; + uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4]; + uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2; + uint32_t pdr_ctl; + uint32_t byp_ctl; + + if ((mmio_read_32(0xFFF00044) & 0x000000FF) == 0x00000000) { + pdqsr_ctl = 1; + lcdl_ctl = 1; + pdr_ctl = 1; + byp_ctl = 1; + } else { + pdqsr_ctl = 0; + lcdl_ctl = 0; + pdr_ctl = 0; + byp_ctl = 0; + } + + /* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */ + ddr_md = (mmio_read_32(RST_MODEMR) >> 19) & BIT(0); + + /* 1584Mbps setting */ + if (ddr_md == 0) { + mmio_write_32(CPG_CPGWPR, 0x5A5AFFFF); + mmio_write_32(CPG_CPGWPCR, 0xA5A50000); + + mmio_write_32(CPG_SRCR4, 0x20000000); + + mmio_write_32(0xE61500DC, 0xe2200000); /* Change to 1584Mbps */ + while (!(mmio_read_32(CPG_PLLECR) & BIT(11))) + ; + + mmio_write_32(CPG_SRSTCLR4, 0x20000000); + + mmio_write_32(CPG_CPGWPCR, 0xA5A50001); + } + + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + mmio_write_32(DBSC_DBKIND, 0x00000007); #if RCAR_DRAM_DDR3L_MEMCONF == 0 - WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02); + mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a02); #else - WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); + mmio_write_32(DBSC_DBMEMCONF00, 0x10030a02); #endif -/* rev.0.08 */ #if RCAR_DRAM_DDR3L_MEMDUAL == 1 - RegVal_R2 = (ReadReg_32(0xE6790614)); - WriteReg_32(0xE6790614, RegVal_R2 | 0x00000003); /* MCS1_N/MODT1 are activated. */ + r2 = mmio_read_32(0xE6790614); + mmio_write_32(0xE6790614, r2 | 0x3); /* MCS1_N/MODT1 are activated. */ #endif - WriteReg_32(DBSC_E3_DBPHYCONF0, 0x00000001); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBTR0, 0x0000000B); - WriteReg_32(DBSC_E3_DBTR1, 0x00000008); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBTR0, 0x0000000D); - WriteReg_32(DBSC_E3_DBTR1, 0x00000009); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBTR2, 0x00000000); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBTR3, 0x0000000B); - WriteReg_32(DBSC_E3_DBTR4, 0x000B000B); - WriteReg_32(DBSC_E3_DBTR5, 0x00000027); - WriteReg_32(DBSC_E3_DBTR6, 0x0000001C); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBTR3, 0x0000000D); - WriteReg_32(DBSC_E3_DBTR4, 0x000D000D); - WriteReg_32(DBSC_E3_DBTR5, 0x0000002D); - WriteReg_32(DBSC_E3_DBTR6, 0x00000020); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBTR7, 0x00060006); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBTR8, 0x00000020); - WriteReg_32(DBSC_E3_DBTR9, 0x00000006); - WriteReg_32(DBSC_E3_DBTR10, 0x0000000C); - WriteReg_32(DBSC_E3_DBTR11, 0x0000000A); - WriteReg_32(DBSC_E3_DBTR12, 0x00120012); - WriteReg_32(DBSC_E3_DBTR13, 0x000000CE); - WriteReg_32(DBSC_E3_DBTR14, 0x00140005); - WriteReg_32(DBSC_E3_DBTR15, 0x00050004); - WriteReg_32(DBSC_E3_DBTR16, 0x071F0305); - WriteReg_32(DBSC_E3_DBTR17, 0x040C0000); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBTR8, 0x00000021); - WriteReg_32(DBSC_E3_DBTR9, 0x00000007); - WriteReg_32(DBSC_E3_DBTR10, 0x0000000E); - WriteReg_32(DBSC_E3_DBTR11, 0x0000000C); - WriteReg_32(DBSC_E3_DBTR12, 0x00140014); - WriteReg_32(DBSC_E3_DBTR13, 0x000000F2); - WriteReg_32(DBSC_E3_DBTR14, 0x00170006); - WriteReg_32(DBSC_E3_DBTR15, 0x00060005); - WriteReg_32(DBSC_E3_DBTR16, 0x09210507); - WriteReg_32(DBSC_E3_DBTR17, 0x040E0000); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBTR18, 0x00000200); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBTR19, 0x01000040); - WriteReg_32(DBSC_E3_DBTR20, 0x020000D6); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBTR19, 0x0129004B); - WriteReg_32(DBSC_E3_DBTR20, 0x020000FB); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBTR21, 0x00040004); - WriteReg_32(DBSC_E3_DBBL, 0x00000000); - WriteReg_32(DBSC_E3_DBODT0, 0x00000001); - WriteReg_32(DBSC_E3_DBADJ0, 0x00000001); - WriteReg_32(DBSC_E3_DBSYSCONF1, 0x00000002); - WriteReg_32(DBSC_E3_DBDFICNT0, 0x00000010); - WriteReg_32(DBSC_E3_DBBCAMDIS, 0x00000001); - WriteReg_32(DBSC_E3_DBSCHRW1, 0x00000046); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_SCFCTST0, 0x0D050B03); - WriteReg_32(DBSC_E3_SCFCTST1, 0x0306030C); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_SCFCTST0, 0x0C050B03); - WriteReg_32(DBSC_E3_SCFCTST1, 0x0305030C); - } /* ddr_md */ - - /**************************************************************************** - * recovery_Step1(PHY setting 1) - ***************************************************************************/ - WriteReg_32(DBSC_E3_DBPDLK0, 0x0000A55A); - WriteReg_32(DBSC_E3_DBCMD, 0x01840001); - WriteReg_32(DBSC_E3_DBCMD, 0x0A840000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000008); /* DDR_PLLCR */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x000B8000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003); /* DDR_PGCR1 */ - if (byp_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C720); - } else { - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C700); - } - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000020); /* DDR_DXCCR */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00181884); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000001A); /* DDR_ACIOCR0 */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x33C03C10); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007); - while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000004); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 792 / 125) - 400 + 0x08B00000); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 928 / 125) - 400 + 0x0A300000); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000022); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x1000040B); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000023); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x2D9C0B66); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x35A00D77); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000024); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A88B400); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A8A2C28); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000025); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005200); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005E00); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000026); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014A9C9); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014CB49); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000027); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000D70); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000F14); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000028); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000046); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000029); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - if (REFRESH_RATE > 3900) { - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000018); /* [7]SRT=0 */ - } else { - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000098); /* [7]SRT=1 */ - } - } else { /* 1856Mbps */ - if (REFRESH_RATE > 3900) { - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000020); /* [7]SRT=0 */ - } else { - WriteReg_32(DBSC_E3_DBPDRGD0, 0x000000A0); /* [7]SRT=1 */ - } /* REFRESH_RATE */ - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003047); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000091); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000095); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BBAD); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000099); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021); /* DDR_DSGCR */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024641E); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x40010000); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000092); /* DDR_ZQ0DR */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0xC2C59AB5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000096); /* DDR_ZQ1DR */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0xC4285FBF); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000009A); /* DDR_ZQ2DR */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0xC2C59AB5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00050001); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - /* ddr backupmode end */ - if (ddrBackup) { - NOTICE("BL2: [WARM_BOOT]\n"); - } else { - NOTICE("BL2: [COLD_BOOT]\n"); - } /* ddrBackup */ - err = rcar_dram_update_boot_status(ddrBackup); - if (err) { - NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n"); - return INITDRAM_ERR_I; - } /* err */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000092); /* DDR_ZQ0DR */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x02C59AB5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000096); /* DDR_ZQ1DR */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x04285FBF); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000009A); /* DDR_ZQ2DR */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x02C59AB5); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x08000000); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000003); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x80010000); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010073); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00); - } /* ddr_md */ - -/* rev0.08 */ - WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000000C); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x18000040); - - /**************************************************************************** - * recovery_Step2(PHY setting 2) - ***************************************************************************/ - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A7); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A8); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A9); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C7); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C8); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C9); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E7); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E8); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E9); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000107); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000108); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000109); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); - - WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000 / REFRESH_RATE) + 0x01000000); - WriteReg_32(DBSC_E3_DBBUS0CNF1, 0x00000010); - - /* Select setting value in bps */ - if (ddr_md == 0) { /* 1584Mbps */ - WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 99 / 125) + 0x00080000); - } else { /* 1856Mbps */ - WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 116 / 125) + 0x00080000); - } /* ddr_md */ - - WriteReg_32(DBSC_E3_DBRFCNF2, 0x00010000); - WriteReg_32(DBSC_E3_DBRFEN, 0x00000001); - WriteReg_32(DBSC_E3_DBCMD, 0x0A840001); - while ((BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0); - - WriteReg_32(DBSC_E3_DBCMD, 0x00000000); - - WriteReg_32(DBSC_E3_DBCMD, 0x04840010); - while ((BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010701); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - for (i = 0; i < 4; i++) - { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20); - RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8; - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20); - RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20); - RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007); - - if (RegVal_R6 > 0) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); - RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R6); - } else { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); - RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R7); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF)); - } /* RegVal_R6 */ - } /* for i */ - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005); - WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00C0); - - /* rev.0.08 */ - if (pdqsr_ctl == 1){} else { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - } - - /* PDR always off */ /* rev.0.10 */ - if (pdr_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - } - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010801); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005); - WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00D8); - - /* rev.0.08 */ - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00011001); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - -if (pdqsr_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); -} - - /* PDR dynamic */ /* rev.0.10 */ - if (pdr_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - } - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00012001); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - -if (pdqsr_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); -} - - /* PDR always off */ /* rev.0.10 */ - if (pdr_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - } - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00014001); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - -if (pdqsr_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); -} - - /* PDR dynamic */ /* rev.0.10 */ - if (pdr_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - } - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00018001); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003087); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010401); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - - for (i = 0; i < 4; i++) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20); - RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20); - RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20); - RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007); - RegVal_R12 = (RegVal_R5 >> 0x2); - - if (RegVal_R12 < RegVal_R6) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); - RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF)); - } else { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); - RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | (RegVal_R7 & 0x00000007)); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF)); - } /* RegVal_R12 < RegVal_R6 */ - } /* for i */ - -/* rev.0.08 */ - if (pdqsr_ctl == 1){} else { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - } - - /* PDR always off */ /* rev.0.10 */ - if (pdr_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); - } - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00015001); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); - while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); - -/* rev.0.08 */ - if (lcdl_ctl == 1) { - for (i = 0; i < 4; i++) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20); - bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8); - bdlcount_0c_div2 = (bdlcount_0c >> 1); - bdlcount_0c_div4 = (bdlcount_0c >> 2); - bdlcount_0c_div8 = (bdlcount_0c >> 3); - bdlcount_0c_div16 = (bdlcount_0c >> 4); - - if (ddr_md == 0) { /* 1584Mbps */ - lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8; - lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16; - } else { /* 1856Mbps */ - lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4; - lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4; - } /* ddr_md */ - - if (dqsgd_0c > lcdl_judge1) { - if (dqsgd_0c <= lcdl_judge2) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_E3_DBPDRGD0, ((dqsgd_0c - bdlcount_0c_div8) | RegVal)); - } else { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); - RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); - gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); - RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal | (gatesl_0c + 1))); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20); - RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0)); - rdqsd_0c = (RegVal & 0x0000FF00) >> 8; - rdqsnd_0c = (RegVal & 0x00FF0000) >> 16; - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20); - WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF) | ((rdqsd_0c + bdlcount_0c_div4) << 8) | ((rdqsnd_0c + bdlcount_0c_div4) << 16))); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20); - RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0)); - rbd_0c[0] = (RegVal) &0x0000001f; - rbd_0c[1] = (RegVal >> 8) & 0x0000001f; - rbd_0c[2] = (RegVal >> 16) & 0x0000001f; - rbd_0c[3] = (RegVal >> 24) & 0x0000001f; - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20); - RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0); - for (j = 0; j < 4; j++) { - rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); - if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; - RegVal = RegVal | (rbd_0c[j] << 8 * j); + mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBTR0, 0x0000000B); + mmio_write_32(DBSC_DBTR1, 0x00000008); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBTR0, 0x0000000D); + mmio_write_32(DBSC_DBTR1, 0x00000009); + } + + mmio_write_32(DBSC_DBTR2, 0x00000000); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBTR3, 0x0000000B); + mmio_write_32(DBSC_DBTR4, 0x000B000B); + mmio_write_32(DBSC_DBTR5, 0x00000027); + mmio_write_32(DBSC_DBTR6, 0x0000001C); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBTR3, 0x0000000D); + mmio_write_32(DBSC_DBTR4, 0x000D000D); + mmio_write_32(DBSC_DBTR5, 0x0000002D); + mmio_write_32(DBSC_DBTR6, 0x00000020); + } + + mmio_write_32(DBSC_DBTR7, 0x00060006); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBTR8, 0x00000020); + mmio_write_32(DBSC_DBTR9, 0x00000006); + mmio_write_32(DBSC_DBTR10, 0x0000000C); + mmio_write_32(DBSC_DBTR11, 0x0000000A); + mmio_write_32(DBSC_DBTR12, 0x00120012); + mmio_write_32(DBSC_DBTR13, 0x000000CE); + mmio_write_32(DBSC_DBTR14, 0x00140005); + mmio_write_32(DBSC_DBTR15, 0x00050004); + mmio_write_32(DBSC_DBTR16, 0x071F0305); + mmio_write_32(DBSC_DBTR17, 0x040C0000); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBTR8, 0x00000021); + mmio_write_32(DBSC_DBTR9, 0x00000007); + mmio_write_32(DBSC_DBTR10, 0x0000000E); + mmio_write_32(DBSC_DBTR11, 0x0000000C); + mmio_write_32(DBSC_DBTR12, 0x00140014); + mmio_write_32(DBSC_DBTR13, 0x000000F2); + mmio_write_32(DBSC_DBTR14, 0x00170006); + mmio_write_32(DBSC_DBTR15, 0x00060005); + mmio_write_32(DBSC_DBTR16, 0x09210507); + mmio_write_32(DBSC_DBTR17, 0x040E0000); + } + + mmio_write_32(DBSC_DBTR18, 0x00000200); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBTR19, 0x01000040); + mmio_write_32(DBSC_DBTR20, 0x020000D6); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBTR19, 0x0129004B); + mmio_write_32(DBSC_DBTR20, 0x020000FB); + } + + mmio_write_32(DBSC_DBTR21, 0x00040004); + mmio_write_32(DBSC_DBBL, 0x00000000); + mmio_write_32(DBSC_DBODT0, 0x00000001); + mmio_write_32(DBSC_DBADJ0, 0x00000001); + mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); + mmio_write_32(DBSC_DBDFICNT0, 0x00000010); + mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); + mmio_write_32(DBSC_DBSCHRW1, 0x00000046); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_SCFCTST0, 0x0D050B03); + mmio_write_32(DBSC_SCFCTST1, 0x0306030C); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_SCFCTST0, 0x0C050B03); + mmio_write_32(DBSC_SCFCTST1, 0x0305030C); + } + + /* + * recovery_Step1(PHY setting 1) + */ + mmio_write_32(DBSC_DBPDLK0, 0x0000A55A); + mmio_write_32(DBSC_DBCMD, 0x01840001); + mmio_write_32(DBSC_DBCMD, 0x0A840000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000008); /* DDR_PLLCR */ + mmio_write_32(DBSC_DBPDRGD0, 0x000B8000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000003); /* DDR_PGCR1 */ + if (byp_ctl == 1) + mmio_write_32(DBSC_DBPDRGD0, 0x0780C720); + else + mmio_write_32(DBSC_DBPDRGD0, 0x0780C700); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000020); /* DDR_DXCCR */ + mmio_write_32(DBSC_DBPDRGD0, 0x00181884); + mmio_write_32(DBSC_DBPDRGA0, 0x0000001A); /* DDR_ACIOCR0 */ + mmio_write_32(DBSC_DBPDRGD0, 0x33C03C10); + mmio_write_32(DBSC_DBPDRGA0, 0x00000007); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000004); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 792 / 125) - + 400 + 0x08B00000); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD0, (REFRESH_RATE * 928 / 125) - + 400 + 0x0A300000); + } + + mmio_write_32(DBSC_DBPDRGA0, 0x00000022); + mmio_write_32(DBSC_DBPDRGD0, 0x1000040B); + mmio_write_32(DBSC_DBPDRGA0, 0x00000023); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x35A00D77); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000024); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x2A88B400); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x2A8A2C28); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000025); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x30005200); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x30005E00); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000026); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x0014CB49); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000027); + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x00000D70); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x00000F14); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000028); + mmio_write_32(DBSC_DBPDRGD0, 0x00000046); + mmio_write_32(DBSC_DBPDRGA0, 0x00000029); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + if (REFRESH_RATE > 3900) + mmio_write_32(DBSC_DBPDRGD0, 0x18); /* [7]SRT=0 */ + else + mmio_write_32(DBSC_DBPDRGD0, 0x98); /* [7]SRT=1 */ + } else { /* 1856Mbps */ + if (REFRESH_RATE > 3900) + mmio_write_32(DBSC_DBPDRGD0, 0x20); /* [7]SRT=0 */ + else + mmio_write_32(DBSC_DBPDRGD0, 0xA0); /* [7]SRT=1 */ + } + + mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD0, 0x81003047); + mmio_write_32(DBSC_DBPDRGA0, 0x00000091); + mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA0, 0x00000095); + mmio_write_32(DBSC_DBPDRGD0, 0x0007BBAD); + mmio_write_32(DBSC_DBPDRGA0, 0x00000099); + mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA0, 0x00000021); /* DDR_DSGCR */ + mmio_write_32(DBSC_DBPDRGD0, 0x0024641E); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD0, 0x40010000); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000092); /* DDR_ZQ0DR */ + mmio_write_32(DBSC_DBPDRGD0, 0xC2C59AB5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000096); /* DDR_ZQ1DR */ + mmio_write_32(DBSC_DBPDRGD0, 0xC4285FBF); + mmio_write_32(DBSC_DBPDRGA0, 0x0000009A); /* DDR_ZQ2DR */ + mmio_write_32(DBSC_DBPDRGD0, 0xC2C59AB5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x0C058900); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x04058900); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x04058A00); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD0, 0x00050001); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + /* ddr backupmode end */ + if (ddr_backup) + NOTICE("BL2: [WARM_BOOT]\n"); + else + NOTICE("BL2: [COLD_BOOT]\n"); + + err = rcar_dram_update_boot_status(ddr_backup); + if (err) { + NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n"); + return INITDRAM_ERR_I; + } + + mmio_write_32(DBSC_DBPDRGA0, 0x00000092); /* DDR_ZQ0DR */ + mmio_write_32(DBSC_DBPDRGD0, 0x02C59AB5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000096); /* DDR_ZQ1DR */ + mmio_write_32(DBSC_DBPDRGD0, 0x04285FBF); + mmio_write_32(DBSC_DBPDRGA0, 0x0000009A); /* DDR_ZQ2DR */ + mmio_write_32(DBSC_DBPDRGD0, 0x02C59AB5); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD0, 0x08000000); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD0, 0x00000003); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD0, 0x80010000); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD0, 0x00010073); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x0C058900); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x0C058A00); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ + + /* Select setting value in bps */ + if (ddr_md == 0) /* 1584Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x04058900); + else /* 1856Mbps */ + mmio_write_32(DBSC_DBPDRGD0, 0x04058A00); + + mmio_write_32(DBSC_DBPDRGA0, 0x0000000C); + mmio_write_32(DBSC_DBPDRGD0, 0x18000040); + + /* + * recovery_Step2(PHY setting 2) + */ + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x000000A7); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000A8); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000A9); + mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C7); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C8); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C9); + mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E7); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E8); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E9); + mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x00000107); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x00000108); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x00000109); + mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); + + mmio_write_32(DBSC_DBCALCNF, (64000000 / REFRESH_RATE) + 0x01000000); + mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); + + /* Select setting value in bps */ + if (ddr_md == 0) { /* 1584Mbps */ + mmio_write_32(DBSC_DBRFCNF1, + (REFRESH_RATE * 99 / 125) + 0x00080000); + } else { /* 1856Mbps */ + mmio_write_32(DBSC_DBRFCNF1, + (REFRESH_RATE * 116 / 125) + 0x00080000); + } + + mmio_write_32(DBSC_DBRFCNF2, 0x00010000); + mmio_write_32(DBSC_DBRFEN, 0x00000001); + mmio_write_32(DBSC_DBCMD, 0x0A840001); + while (mmio_read_32(DBSC_DBWAIT) & BIT(0)) + ; + + mmio_write_32(DBSC_DBCMD, 0x00000000); + + mmio_write_32(DBSC_DBCMD, 0x04840010); + while (mmio_read_32(DBSC_DBWAIT) & BIT(0)) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); /* DDR_PIR */ + mmio_write_32(DBSC_DBPDRGD0, 0x00010701); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + for (i = 0; i < 4; i++) { + mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8; + mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + + if (r6 > 0) { + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | r6); + } else { + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | r7); + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, + r2 | ((r6 + (r5 << 1)) & 0xFF)); } - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20); - RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0)); - rbd_0c[0] = (RegVal) &0x0000001f; - rbd_0c[1] = (RegVal >> 8) & 0x0000001f; - rbd_0c[2] = (RegVal >> 16) & 0x0000001f; - rbd_0c[3] = (RegVal >> 24) & 0x0000001f; - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20); - RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0); - for (j = 0; j < 4; j++) { - rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); - if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; - RegVal = RegVal | (rbd_0c[j] << 8 * j); + } + + mmio_write_32(DBSC_DBPDRGA0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00C0); + + if (pdqsr_ctl == 0) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + } + + /* PDR always off */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + } + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010801); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00D8); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00011001); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + if (pdqsr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + } + + /* PDR dynamic */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + } + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00012001); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + if (pdqsr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + } + + /* PDR always off */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + } + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00014001); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + if (pdqsr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + } + + /* PDR dynamic */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + } + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00018001); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD0, 0x81003087); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010401); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + for (i = 0; i < 4; i++) { + mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); + r5 = ((mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 0x8); + mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + r12 = r5 >> 0x2; + + if (r12 < r6) { + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | ((r7 + 0x1) & 0x7)); + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | ((r6 - r12) & 0xFF)); + } else { + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | (r7 & 0x7)); + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + r2 = mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, + r2 | + ((r6 + r5 + (r5 >> 1) + r12) & 0xFF)); } - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); - } - } - } - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000002); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x07D81E37); - } - - - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003); - if (byp_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C720); - } else { - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C700); - } - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007); - while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024643E); - - /**************************************************************************** - * recovery_Step3(DBSC Setting 2) - ***************************************************************************/ - WriteReg_32(DBSC_E3_DBDFICUPDCNF, 0x40100001); - WriteReg_32(DBSC_E3_DBACEN, 0x00000001); - -/* rev.0.08 */ - if (pdqsr_ctl == 1) { - WriteReg_32(0xE67F0018, 0x00000001); - RegVal = ReadReg_32(0x40000000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000000); - WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); - } - - /* PDR dynamic */ /* rev.0.10 */ - if (pdr_ctl == 1) { - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); - WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); - } - - WriteReg_32(DBSC_E3_DBPDLK0, 0x00000000); - WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000); - -#ifdef ddr_qos_init_setting /* only for non qos_init */ - WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234); - WriteReg_32(DBSC_E3_DBCAM0CNF1, 0x00043218); - WriteReg_32(DBSC_E3_DBCAM0CNF2, 0x000000F4); - WriteReg_32(DBSC_E3_DBSCHCNT0, 0x000f0037); - WriteReg_32(DBSC_E3_DBSCHSZ0, 0x00000001); - WriteReg_32(DBSC_E3_DBSCHRW0, 0x22421111); - WriteReg_32(DBSC_E3_SCFCTST2, 0x012F1123); - WriteReg_32(DBSC_E3_DBSCHQOS00, 0x00000F00); - WriteReg_32(DBSC_E3_DBSCHQOS01, 0x00000B00); - WriteReg_32(DBSC_E3_DBSCHQOS02, 0x00000000); - WriteReg_32(DBSC_E3_DBSCHQOS03, 0x00000000); - WriteReg_32(DBSC_E3_DBSCHQOS40, 0x00000300); - WriteReg_32(DBSC_E3_DBSCHQOS41, 0x000002F0); - WriteReg_32(DBSC_E3_DBSCHQOS42, 0x00000200); - WriteReg_32(DBSC_E3_DBSCHQOS43, 0x00000100); - WriteReg_32(DBSC_E3_DBSCHQOS90, 0x00000100); - WriteReg_32(DBSC_E3_DBSCHQOS91, 0x000000F0); - WriteReg_32(DBSC_E3_DBSCHQOS92, 0x000000A0); - WriteReg_32(DBSC_E3_DBSCHQOS93, 0x00000040); - WriteReg_32(DBSC_E3_DBSCHQOS130, 0x00000100); - WriteReg_32(DBSC_E3_DBSCHQOS131, 0x000000F0); - WriteReg_32(DBSC_E3_DBSCHQOS132, 0x000000A0); - WriteReg_32(DBSC_E3_DBSCHQOS133, 0x00000040); - WriteReg_32(DBSC_E3_DBSCHQOS140, 0x000000C0); - WriteReg_32(DBSC_E3_DBSCHQOS141, 0x000000B0); - WriteReg_32(DBSC_E3_DBSCHQOS142, 0x00000080); - WriteReg_32(DBSC_E3_DBSCHQOS143, 0x00000040); - WriteReg_32(DBSC_E3_DBSCHQOS150, 0x00000040); - WriteReg_32(DBSC_E3_DBSCHQOS151, 0x00000030); - WriteReg_32(DBSC_E3_DBSCHQOS152, 0x00000020); - WriteReg_32(DBSC_E3_DBSCHQOS153, 0x00000010); - -/* rev.0.08 */ - if (pdqsr_ctl == 1){} else { - WriteReg_32(0xE67F0018, 0x00000001); - } - - WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000); + } + + if (pdqsr_ctl == 0) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + } + + /* PDR always off */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + mmio_write_32(DBSC_DBPDRGA0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD0, 0x00000008); + } + + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00015001); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; + + if (lcdl_ctl == 1) { + for (i = 0; i < 4; i++) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000B0 + i * 0x20); + dqsgd_0c = mmio_read_32(DBSC_DBPDRGD0) & 0x000000FF; + mmio_write_32(DBSC_DBPDRGA0, 0x000000B1 + i * 0x20); + bdlcount_0c = (mmio_read_32(DBSC_DBPDRGD0) & + 0x0000FF00) >> 8; + bdlcount_0c_div2 = (bdlcount_0c >> 1); + bdlcount_0c_div4 = (bdlcount_0c >> 2); + bdlcount_0c_div8 = (bdlcount_0c >> 3); + bdlcount_0c_div16 = (bdlcount_0c >> 4); + + if (ddr_md == 0) { /* 1584Mbps */ + lcdl_judge1 = bdlcount_0c_div2 + + bdlcount_0c_div4 + + bdlcount_0c_div8; + lcdl_judge2 = bdlcount_0c + + bdlcount_0c_div4 + + bdlcount_0c_div16; + } else { /* 1856Mbps */ + lcdl_judge1 = bdlcount_0c_div2 + + bdlcount_0c_div4; + lcdl_judge2 = bdlcount_0c + + bdlcount_0c_div4; + } + + if (dqsgd_0c <= lcdl_judge1) + continue; + + if (dqsgd_0c <= lcdl_judge2) { + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD0) & + 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGD0, + (dqsgd_0c - bdlcount_0c_div8) | + regval); + } else { + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD0) & + 0xFFFFFF00; + mmio_write_32(DBSC_DBPDRGD0, regval); + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + gatesl_0c = mmio_read_32(DBSC_DBPDRGD0) & 0x7; + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD0) & + 0xFFFFFFF8; + mmio_write_32(DBSC_DBPDRGD0, + regval | (gatesl_0c + 1)); + mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD0); + rdqsd_0c = (regval & 0xFF00) >> 8; + rdqsnd_0c = (regval & 0xFF0000) >> 16; + mmio_write_32(DBSC_DBPDRGA0, 0xAF + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, + (regval & 0xFF0000FF) | + ((rdqsd_0c + + bdlcount_0c_div4) << 8) | + ((rdqsnd_0c + + bdlcount_0c_div4) << 16)); + mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20); + regval = (mmio_read_32(DBSC_DBPDRGD0)); + rbd_0c[0] = (regval) & 0x1f; + rbd_0c[1] = (regval >> 8) & 0x1f; + rbd_0c[2] = (regval >> 16) & 0x1f; + rbd_0c[3] = (regval >> 24) & 0x1f; + mmio_write_32(DBSC_DBPDRGA0, 0xAA + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD0) & + 0xE0E0E0E0; + for (j = 0; j < 4; j++) { + rbd_0c[j] = rbd_0c[j] + + bdlcount_0c_div4; + if (rbd_0c[j] > 0x1F) + rbd_0c[j] = 0x1F; + regval = regval | (rbd_0c[j] << 8 * j); + } + mmio_write_32(DBSC_DBPDRGD0, regval); + mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20); + regval = (mmio_read_32(DBSC_DBPDRGD0)); + rbd_0c[0] = regval & 0x1f; + rbd_0c[1] = (regval >> 8) & 0x1f; + rbd_0c[2] = (regval >> 16) & 0x1f; + rbd_0c[3] = (regval >> 24) & 0x1f; + mmio_write_32(DBSC_DBPDRGA0, 0xAB + i * 0x20); + regval = mmio_read_32(DBSC_DBPDRGD0) & + 0xE0E0E0E0; + for (j = 0; j < 4; j++) { + rbd_0c[j] = rbd_0c[j] + + bdlcount_0c_div4; + if (rbd_0c[j] > 0x1F) + rbd_0c[j] = 0x1F; + regval = regval | (rbd_0c[j] << 8 * j); + } + mmio_write_32(DBSC_DBPDRGD0, regval); + } + } + mmio_write_32(DBSC_DBPDRGA0, 0x00000002); + mmio_write_32(DBSC_DBPDRGD0, 0x07D81E37); + } + + mmio_write_32(DBSC_DBPDRGA0, 0x00000003); + if (byp_ctl == 1) + mmio_write_32(DBSC_DBPDRGD0, 0x0380C720); + else + mmio_write_32(DBSC_DBPDRGD0, 0x0380C700); + + mmio_write_32(DBSC_DBPDRGA0, 0x00000007); + while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30)) + ; + mmio_write_32(DBSC_DBPDRGA0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD0, 0x0024643E); + + /* + * recovery_Step3(DBSC Setting 2) + */ + mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); + mmio_write_32(DBSC_DBACEN, 0x00000001); + + if (pdqsr_ctl == 1) { + mmio_write_32(0xE67F0018, 0x00000001); + regval = mmio_read_32(0x40000000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000000); + mmio_write_32(DBSC_DBPDRGD0, regval); + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + } + + /* PDR dynamic */ + if (pdr_ctl == 1) { + mmio_write_32(DBSC_DBPDRGA0, 0x000000A3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E3); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000103); + mmio_write_32(DBSC_DBPDRGD0, 0x00000000); + } + + mmio_write_32(DBSC_DBPDLK0, 0x00000000); + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); + +#ifdef ddr_qos_init_setting /* only for non qos_init */ + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); + mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4); + mmio_write_32(DBSC_DBSCHCNT0, 0x000f0037); + mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); + mmio_write_32(DBSC_DBSCHRW0, 0x22421111); + mmio_write_32(DBSC_SCFCTST2, 0x012F1123); + mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00); + mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00); + mmio_write_32(DBSC_DBSCHQOS02, 0x00000000); + mmio_write_32(DBSC_DBSCHQOS03, 0x00000000); + mmio_write_32(DBSC_DBSCHQOS40, 0x00000300); + mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0); + mmio_write_32(DBSC_DBSCHQOS42, 0x00000200); + mmio_write_32(DBSC_DBSCHQOS43, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS90, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0); + mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0); + mmio_write_32(DBSC_DBSCHQOS93, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS130, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0); + mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0); + mmio_write_32(DBSC_DBSCHQOS133, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0); + mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0); + mmio_write_32(DBSC_DBSCHQOS142, 0x00000080); + mmio_write_32(DBSC_DBSCHQOS143, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS150, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS151, 0x00000030); + mmio_write_32(DBSC_DBSCHQOS152, 0x00000020); + mmio_write_32(DBSC_DBSCHQOS153, 0x00000010); + + if (pdqsr_ctl == 0) + mmio_write_32(0xE67F0018, 0x00000001); + + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); #endif - return 1; + return 1; -} /* recovery_from_backup_mode */ +} /* recovery_from_backup_mode */ -/******************************************************************************* - * init_ddr : MD19=0,DDR3L,1584Mbps / MD19=1,DDR3L,1856Mbps - ******************************************************************************/ +/* + * init_ddr : MD19=0,DDR3L,1584Mbps / MD19=1,DDR3L,1856Mbps + */ -/******************************************************************************* - * DDR Initialize entry for IPL - ******************************************************************************/ +/* + * DDR Initialize entry for IPL + */ int32_t rcar_dram_init(void) { - uint32_t dataL; - uint32_t failcount; - uint32_t md = 0; - uint32_t ddr = 0; - - md = *((volatile uint32_t*)RST_MODEMR); - ddr = (md & 0x00080000) >> 19; - if (ddr == 0x0) { - NOTICE("BL2: DDR1584(%s)\n", RCAR_E3_DDR_VERSION); - } else if(ddr == 0x1){ - NOTICE("BL2: DDR1856(%s)\n", RCAR_E3_DDR_VERSION); - } /* ddr */ - - rcar_dram_get_boot_status(&ddrBackup); - - if (ddrBackup == DRAM_BOOT_STATUS_WARM) { - dataL = recovery_from_backup_mode(); /* WARM boot */ - } else { - dataL = init_ddr(); /* COLD boot */ - } /* ddrBackup */ - - if (dataL == 1) { - failcount = 0; - } else { - failcount = 1; - } /* dataL */ - - if (failcount == 0) { - return INITDRAM_OK; - } else { - return INITDRAM_NG; - } /* failcount */ -} /* InitDram */ - -/******************************************************************************* - * END - ******************************************************************************/ + uint32_t dataL; + uint32_t failcount; + uint32_t md = 0; + uint32_t ddr = 0; + uint32_t ddr_backup; + + md = *((volatile uint32_t*)RST_MODEMR); + ddr = (md & 0x00080000) >> 19; + if (ddr == 0x0) + NOTICE("BL2: DDR1584(%s)\n", RCAR_E3_DDR_VERSION); + else if (ddr == 0x1) + NOTICE("BL2: DDR1856(%s)\n", RCAR_E3_DDR_VERSION); + + rcar_dram_get_boot_status(&ddr_backup); + + if (ddr_backup == DRAM_BOOT_STATUS_WARM) + dataL = recovery_from_backup_mode(ddr_backup); /* WARM boot */ + else + dataL = init_ddr(); /* COLD boot */ + + if (dataL == 1) + failcount = 0; + else + failcount = 1; + + if (failcount == 0) + return INITDRAM_OK; + else + return INITDRAM_NG; + +} diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h deleted file mode 100644 index 1a96a69c7c..0000000000 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef DDR_INIT_E3_H -#define DDR_INIT_E3_H - -#include <stdint.h> - -#define RCAR_E3_DDR_VERSION "rev.0.12" - -#ifdef ddr_qos_init_setting - #define REFRESH_RATE 3900 /* Average periodic refresh interval[ns]. Support 3900,7800 */ -#else - #if RCAR_REF_INT == 0 - #define REFRESH_RATE 3900 - #elif RCAR_REF_INT == 1 - #define REFRESH_RATE 7800 - #else - #define REFRESH_RATE 3900 - #endif -#endif - -extern int32_t rcar_dram_init(void); -#define INITDRAM_OK (0) -#define INITDRAM_NG (0xffffffff) -#define INITDRAM_ERR_I (0xffffffff) -#define INITDRAM_ERR_O (0xfffffffe) -#define INITDRAM_ERR_T (0xfffffff0) - -#endif /* DDR_INIT_E3_H */ diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c index 7e93328604..00e1903ce1 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c @@ -1,339 +1,338 @@ /* - * Copyright (c) 2015-2016, Renesas Electronics Corporation + * Copyright (c) 2015-2019, Renesas Electronics Corporation * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include <lib/mmio.h> +#include <lib/utils_def.h> #include <stdint.h> #include "boot_init_dram.h" -#include "boot_init_dram_regdef_v3m.h" - -static void WriteReg_32(uintptr_t a, uint32_t v) -{ - *(volatile uint32_t*)a = v; -} - -static uint32_t ReadReg_32(uintptr_t a) -{ - uint32_t w = *(volatile uint32_t*)a; - return w; -} +#include "boot_init_dram_regdef.h" static uint32_t init_ddr_v3m_1600(void) { - // last modified 2016.12.16 + uint32_t i, r2, r5, r6, r7, r12; - uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12; - - WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234); - WriteReg_32(DBSC_V3M_DBKIND,0x00000007); + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + mmio_write_32(DBSC_DBKIND, 0x00000007); #if RCAR_DRAM_DDR3L_MEMCONF == 0 - WriteReg_32(DBSC_V3M_DBMEMCONF00,0x0f030a02); // 1GB: Eagle + mmio_write_32(DBSC_DBMEMCONF00, 0x0f030a02); // 1GB: Eagle #else - WriteReg_32(DBSC_V3M_DBMEMCONF00,0x10030a02); // 2GB: V3MSK + mmio_write_32(DBSC_DBMEMCONF00, 0x10030a02); // 2GB: V3MSK #endif - WriteReg_32(DBSC_V3M_DBPHYCONF0,0x00000001); - WriteReg_32(DBSC_V3M_DBTR0,0x0000000B); - WriteReg_32(DBSC_V3M_DBTR1,0x00000008); - WriteReg_32(DBSC_V3M_DBTR3,0x0000000B); - WriteReg_32(DBSC_V3M_DBTR4,0x000B000B); - WriteReg_32(DBSC_V3M_DBTR5,0x00000027); - WriteReg_32(DBSC_V3M_DBTR6,0x0000001C); - WriteReg_32(DBSC_V3M_DBTR7,0x00060006); - WriteReg_32(DBSC_V3M_DBTR8,0x00000020); - WriteReg_32(DBSC_V3M_DBTR9,0x00000006); - WriteReg_32(DBSC_V3M_DBTR10,0x0000000C); - WriteReg_32(DBSC_V3M_DBTR11,0x0000000B); - WriteReg_32(DBSC_V3M_DBTR12,0x00120012); - WriteReg_32(DBSC_V3M_DBTR13,0x01180118); - WriteReg_32(DBSC_V3M_DBTR14,0x00140005); - WriteReg_32(DBSC_V3M_DBTR15,0x00050004); - WriteReg_32(DBSC_V3M_DBTR16,0x071D0305); - WriteReg_32(DBSC_V3M_DBTR17,0x040C0010); - WriteReg_32(DBSC_V3M_DBTR18,0x00000200); - WriteReg_32(DBSC_V3M_DBTR19,0x01000040); - WriteReg_32(DBSC_V3M_DBTR20,0x02000120); - WriteReg_32(DBSC_V3M_DBTR21,0x00040004); - WriteReg_32(DBSC_V3M_DBBL,0x00000000); - WriteReg_32(DBSC_V3M_DBODT0,0x00000001); - WriteReg_32(DBSC_V3M_DBADJ0,0x00000001); - WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00082010); - WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x00002000); - WriteReg_32(DBSC_V3M_DBSCHCNT0,0x080f003f); - WriteReg_32(DBSC_V3M_DBSCHCNT1,0x00001010); - WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000001); - WriteReg_32(DBSC_V3M_DBSCHRW0,0x00000200); - WriteReg_32(DBSC_V3M_DBSCHRW1,0x00000040); - WriteReg_32(DBSC_V3M_DBSCHQOS40,0x00000600); - WriteReg_32(DBSC_V3M_DBSCHQOS41,0x00000480); - WriteReg_32(DBSC_V3M_DBSCHQOS42,0x00000300); - WriteReg_32(DBSC_V3M_DBSCHQOS43,0x00000180); - WriteReg_32(DBSC_V3M_DBSCHQOS90,0x00000400); - WriteReg_32(DBSC_V3M_DBSCHQOS91,0x00000300); - WriteReg_32(DBSC_V3M_DBSCHQOS92,0x00000200); - WriteReg_32(DBSC_V3M_DBSCHQOS93,0x00000100); - WriteReg_32(DBSC_V3M_DBSCHQOS130,0x00000300); - WriteReg_32(DBSC_V3M_DBSCHQOS131,0x00000240); - WriteReg_32(DBSC_V3M_DBSCHQOS132,0x00000180); - WriteReg_32(DBSC_V3M_DBSCHQOS133,0x000000c0); - WriteReg_32(DBSC_V3M_DBSCHQOS140,0x00000200); - WriteReg_32(DBSC_V3M_DBSCHQOS141,0x00000180); - WriteReg_32(DBSC_V3M_DBSCHQOS142,0x00000100); - WriteReg_32(DBSC_V3M_DBSCHQOS143,0x00000080); - WriteReg_32(DBSC_V3M_DBSCHQOS150,0x00000100); - WriteReg_32(DBSC_V3M_DBSCHQOS151,0x000000c0); - WriteReg_32(DBSC_V3M_DBSCHQOS152,0x00000080); - WriteReg_32(DBSC_V3M_DBSCHQOS153,0x00000040); - WriteReg_32(DBSC_V3M_DBSYSCONF1,0x00000002); - WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00040C04); - WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x000001c4); - WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000003); - WriteReg_32(DBSC_V3M_DBSCHRW1,0x001a0080); - WriteReg_32(DBSC_V3M_DBDFICNT0,0x00000010); + mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); + mmio_write_32(DBSC_DBTR0, 0x0000000B); + mmio_write_32(DBSC_DBTR1, 0x00000008); + mmio_write_32(DBSC_DBTR3, 0x0000000B); + mmio_write_32(DBSC_DBTR4, 0x000B000B); + mmio_write_32(DBSC_DBTR5, 0x00000027); + mmio_write_32(DBSC_DBTR6, 0x0000001C); + mmio_write_32(DBSC_DBTR7, 0x00060006); + mmio_write_32(DBSC_DBTR8, 0x00000020); + mmio_write_32(DBSC_DBTR9, 0x00000006); + mmio_write_32(DBSC_DBTR10, 0x0000000C); + mmio_write_32(DBSC_DBTR11, 0x0000000B); + mmio_write_32(DBSC_DBTR12, 0x00120012); + mmio_write_32(DBSC_DBTR13, 0x01180118); + mmio_write_32(DBSC_DBTR14, 0x00140005); + mmio_write_32(DBSC_DBTR15, 0x00050004); + mmio_write_32(DBSC_DBTR16, 0x071D0305); + mmio_write_32(DBSC_DBTR17, 0x040C0010); + mmio_write_32(DBSC_DBTR18, 0x00000200); + mmio_write_32(DBSC_DBTR19, 0x01000040); + mmio_write_32(DBSC_DBTR20, 0x02000120); + mmio_write_32(DBSC_DBTR21, 0x00040004); + mmio_write_32(DBSC_DBBL, 0x00000000); + mmio_write_32(DBSC_DBODT0, 0x00000001); + mmio_write_32(DBSC_DBADJ0, 0x00000001); + mmio_write_32(DBSC_DBCAM0CNF1, 0x00082010); + mmio_write_32(DBSC_DBCAM0CNF2, 0x00002000); + mmio_write_32(DBSC_DBSCHCNT0, 0x080f003f); + mmio_write_32(DBSC_DBSCHCNT1, 0x00001010); + mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); + mmio_write_32(DBSC_DBSCHRW0, 0x00000200); + mmio_write_32(DBSC_DBSCHRW1, 0x00000040); + mmio_write_32(DBSC_DBSCHQOS40, 0x00000600); + mmio_write_32(DBSC_DBSCHQOS41, 0x00000480); + mmio_write_32(DBSC_DBSCHQOS42, 0x00000300); + mmio_write_32(DBSC_DBSCHQOS43, 0x00000180); + mmio_write_32(DBSC_DBSCHQOS90, 0x00000400); + mmio_write_32(DBSC_DBSCHQOS91, 0x00000300); + mmio_write_32(DBSC_DBSCHQOS92, 0x00000200); + mmio_write_32(DBSC_DBSCHQOS93, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS130, 0x00000300); + mmio_write_32(DBSC_DBSCHQOS131, 0x00000240); + mmio_write_32(DBSC_DBSCHQOS132, 0x00000180); + mmio_write_32(DBSC_DBSCHQOS133, 0x000000c0); + mmio_write_32(DBSC_DBSCHQOS140, 0x00000200); + mmio_write_32(DBSC_DBSCHQOS141, 0x00000180); + mmio_write_32(DBSC_DBSCHQOS142, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS143, 0x00000080); + mmio_write_32(DBSC_DBSCHQOS150, 0x00000100); + mmio_write_32(DBSC_DBSCHQOS151, 0x000000c0); + mmio_write_32(DBSC_DBSCHQOS152, 0x00000080); + mmio_write_32(DBSC_DBSCHQOS153, 0x00000040); + mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); + mmio_write_32(DBSC_DBCAM0CNF1, 0x00040C04); + mmio_write_32(DBSC_DBCAM0CNF2, 0x000001c4); + mmio_write_32(DBSC_DBSCHSZ0, 0x00000003); + mmio_write_32(DBSC_DBSCHRW1, 0x001a0080); + mmio_write_32(DBSC_DBDFICNT0, 0x00000010); + + mmio_write_32(DBSC_DBPDLK0, 0x0000A55A); + mmio_write_32(DBSC_DBCMD, 0x01000001); + mmio_write_32(DBSC_DBCMD, 0x08000000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x80010000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; - WriteReg_32(DBSC_V3M_DBPDLK0,0X0000A55A); - WriteReg_32(DBSC_V3M_DBCMD,0x01000001); - WriteReg_32(DBSC_V3M_DBCMD,0x08000000); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X80010000); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); - while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + mmio_write_32(DBSC_DBPDRGA0, 0x00000008); + mmio_write_32(DBSC_DBPDRGD0, 0x000B8000); + mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD0, 0x04058904); + mmio_write_32(DBSC_DBPDRGA0, 0x00000091); + mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6D); + mmio_write_32(DBSC_DBPDRGA0, 0x00000095); + mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6B); + mmio_write_32(DBSC_DBPDRGA0, 0x00000099); + mmio_write_32(DBSC_DBPDRGD0, 0x0007BB6D); + mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD0, 0x04058900); + mmio_write_32(DBSC_DBPDRGA0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD0, 0x0024641E); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010073); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000008); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X000B8000); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058904); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000091); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000095); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6B); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000099); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024641E); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010073); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); - while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD0, 0x0C058900); + mmio_write_32(DBSC_DBPDRGA0, 0x00000090); + mmio_write_32(DBSC_DBPDRGD0, 0x04058900); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X0C058900); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); - while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + mmio_write_32(DBSC_DBPDRGA0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD0, 0x0780C700); + mmio_write_32(DBSC_DBPDRGA0, 0x00000007); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(30))) + ; - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X0780C700); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007); - while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + mmio_write_32(DBSC_DBPDRGA0, 0x00000004); + mmio_write_32(DBSC_DBPDRGD0, 0x08C0C170); + mmio_write_32(DBSC_DBPDRGA0, 0x00000022); + mmio_write_32(DBSC_DBPDRGD0, 0x1000040B); + mmio_write_32(DBSC_DBPDRGA0, 0x00000023); + mmio_write_32(DBSC_DBPDRGD0, 0x2D9C0B66); + mmio_write_32(DBSC_DBPDRGA0, 0x00000024); + mmio_write_32(DBSC_DBPDRGD0, 0x2A88C400); + mmio_write_32(DBSC_DBPDRGA0, 0x00000025); + mmio_write_32(DBSC_DBPDRGD0, 0x30005200); + mmio_write_32(DBSC_DBPDRGA0, 0x00000026); + mmio_write_32(DBSC_DBPDRGD0, 0x0014A9C9); + mmio_write_32(DBSC_DBPDRGA0, 0x00000027); + mmio_write_32(DBSC_DBPDRGD0, 0x00000D70); + mmio_write_32(DBSC_DBPDRGA0, 0x00000028); + mmio_write_32(DBSC_DBPDRGD0, 0x00000004); + mmio_write_32(DBSC_DBPDRGA0, 0x00000029); + mmio_write_32(DBSC_DBPDRGD0, 0x00000018); + mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD0, 0x81003047); + mmio_write_32(DBSC_DBPDRGA0, 0x00000020); + mmio_write_32(DBSC_DBPDRGD0, 0x00181884); + mmio_write_32(DBSC_DBPDRGA0, 0x0000001A); + mmio_write_32(DBSC_DBPDRGD0, 0x13C03C10); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000004); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X08C0C170); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000022); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X1000040B); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000023); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X2D9C0B66); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000024); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X2A88C400); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000025); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X30005200); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000026); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X0014A9C9); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000027); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000D70); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000028); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000004); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000029); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000018); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003047); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000020); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X00181884); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000001A); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X13C03C10); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); - while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + mmio_write_32(DBSC_DBPDRGA0, 0x000000A7); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000A8); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000A9); + mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C7); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C8); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C9); + mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E7); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E8); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E9); + mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x00000107); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x00000108); + mmio_write_32(DBSC_DBPDRGD0, 0x0D0D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x00000109); + mmio_write_32(DBSC_DBPDRGD0, 0x000D0D0D); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010181); + mmio_write_32(DBSC_DBCMD, 0x08000001); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A7); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A8); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A9); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C7); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C8); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C9); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E7); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E8); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E9); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000107); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000108); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000109); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010181); - WriteReg_32(DBSC_V3M_DBCMD,0x08000001); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); - while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010601); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010601); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); - while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + for (i = 0; i < 4; i++) { + mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 8; + mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); + r6 = mmio_read_32(DBSC_DBPDRGD0) & 0xFF; + mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); + r7 = mmio_read_32(DBSC_DBPDRGD0) & 0x7; - for (uint32_t i = 0; i<4; i++) - { - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1 + i*0x20); - RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8; - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4 + i*0x20); - RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ; - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3 + i*0x20); - RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ; - if ( RegVal_R6 > 0 ) - { - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; + if (r6 > 0) { + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); - WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); - WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R6); - } else { - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); - WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R7); + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, ((r7 + 1) & 0x7) | r2); + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00); + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | r6); + } else { + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8); + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | r7); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); - RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); - WriteReg_32(DBSC_V3M_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2); - } - } + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00); + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | + (((r5 << 1) + r6) & 0xFF)); + } + } - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005); - WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00A0); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010801); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); - while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + mmio_write_32(DBSC_DBPDRGA0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00A0); + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010801); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005); - WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00B8); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X0001F001); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); - while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + mmio_write_32(DBSC_DBPDRGA0, 0x00000005); + mmio_write_32(DBSC_DBPDRGD0, 0xC1AA00B8); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x0001F001); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003087); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010401); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); - while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD0, 0x7C000285); + mmio_write_32(DBSC_DBPDRGA0, 0x0000002C); + mmio_write_32(DBSC_DBPDRGD0, 0x81003087); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00010401); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; - for (uint32_t i = 0; i < 4; i++) - { - WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B1 + i * 0x20); - RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8; - WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B4 + i * 0x20); - RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF); + for (i = 0; i < 4; i++) { + mmio_write_32(DBSC_DBPDRGA0, 0xB1 + i * 0x20); + r5 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF00) >> 8; + mmio_write_32(DBSC_DBPDRGA0, 0xB4 + i * 0x20); + r6 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFF); - WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B3 + i * 0x20); - RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007); - RegVal_R12 = (RegVal_R5 >> 2); - if (RegVal_R6 - RegVal_R12 > 0) - { - WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); - RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8); + mmio_write_32(DBSC_DBPDRGA0, 0xB3 + i * 0x20); + r7 = (mmio_read_32(DBSC_DBPDRGD0) & 0x7); + r12 = (r5 >> 2); + if (r6 - r12 > 0) { + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8); - WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); - WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R7 + 1) & 0X00000007) | RegVal_R2); - WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); - RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00); + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, ((r7 + 1) & 0x7) | r2); + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00); - WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); - WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 - RegVal_R12) & 0X000000FF) | RegVal_R2); - } - else - { - WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); - RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8); - WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); - WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal_R7 & 0X00000007) | RegVal_R2); - WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); - RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00); - WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); - WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 + RegVal_R5 + (RegVal_R5 >> 1) + RegVal_R12) & 0X000000FF) | RegVal_R2); - } - } + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, ((r6 - r12) & 0xFF) | r2); + } else { + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFFF8); + mmio_write_32(DBSC_DBPDRGA0, 0xB2 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, (r7 & 0x7) | r2); + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + r2 = (mmio_read_32(DBSC_DBPDRGD0) & 0xFFFFFF00); + mmio_write_32(DBSC_DBPDRGA0, 0xB0 + i * 0x20); + mmio_write_32(DBSC_DBPDRGD0, r2 | + ((r6 + r5 + + (r5 >> 1) + r12) & 0xFF)); + } + } - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X00015001); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); - while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + mmio_write_32(DBSC_DBPDRGA0, 0x000000A0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000C0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x000000E0); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000100); + mmio_write_32(DBSC_DBPDRGD0, 0x7C0002C5); + mmio_write_32(DBSC_DBPDRGA0, 0x00000001); + mmio_write_32(DBSC_DBPDRGD0, 0x00015001); + mmio_write_32(DBSC_DBPDRGA0, 0x00000006); + while (!(mmio_read_32(DBSC_DBPDRGD0) & BIT(0))) + ; - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X0380C700); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007); - while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) != 0 ); - WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021); - WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024643E); + mmio_write_32(DBSC_DBPDRGA0, 0x00000003); + mmio_write_32(DBSC_DBPDRGD0, 0x0380C700); + mmio_write_32(DBSC_DBPDRGA0, 0x00000007); + while (mmio_read_32(DBSC_DBPDRGD0) & BIT(30)) + ; + mmio_write_32(DBSC_DBPDRGA0, 0x00000021); + mmio_write_32(DBSC_DBPDRGD0, 0x0024643E); - WriteReg_32(DBSC_V3M_DBBUS0CNF1,0x00000000); - WriteReg_32(DBSC_V3M_DBBUS0CNF0,0x00010001); - WriteReg_32(DBSC_V3M_DBCALCNF,0x0100200E); - WriteReg_32(DBSC_V3M_DBRFCNF1,0x00081860); - WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000); - WriteReg_32(DBSC_V3M_DBDFICUPDCNF,0x40100001); - WriteReg_32(DBSC_V3M_DBRFEN,0x00000001); - WriteReg_32(DBSC_V3M_DBACEN,0x00000001); - WriteReg_32(DBSC_V3M_DBPDLK0,0X00000000); - WriteReg_32(0xE67F0024, 0x00000001); - WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000); + mmio_write_32(DBSC_DBBUS0CNF1, 0x00000000); + mmio_write_32(DBSC_DBBUS0CNF0, 0x00010001); + mmio_write_32(DBSC_DBCALCNF, 0x0100200E); + mmio_write_32(DBSC_DBRFCNF1, 0x00081860); + mmio_write_32(DBSC_DBRFCNF2, 0x00010000); + mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001); + mmio_write_32(DBSC_DBRFEN, 0x00000001); + mmio_write_32(DBSC_DBACEN, 0x00000001); + mmio_write_32(DBSC_DBPDLK0, 0x00000000); + mmio_write_32(0xE67F0024, 0x00000001); + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); - return 1; + return INITDRAM_OK; } int32_t rcar_dram_init(void) { - return init_ddr_v3m_1600() ? INITDRAM_OK : INITDRAM_NG; + return init_ddr_v3m_1600(); } diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c index 9c53074c27..89d666ce6d 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c @@ -4221,10 +4221,10 @@ int32_t rcar_dram_init(void) Thermal sensor setting ***********************************************************************/ dataL = mmio_read_32(CPG_MSTPSR5); - if (dataL & BIT22) { /* case THS/TSC Standby */ - dataL &= ~(BIT22); + if (dataL & BIT(22)) { /* case THS/TSC Standby */ + dataL &= ~(BIT(22)); cpg_write_32(CPG_SMSTPCR5, dataL); - while ((BIT22) & mmio_read_32(CPG_MSTPSR5)); /* wait bit=0 */ + while ((BIT(22)) & mmio_read_32(CPG_MSTPSR5)); /* wait bit=0 */ } /* THCTR Bit6: PONM=0 , Bit0: THSST=0 */ diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c index 0b10e5ff03..5d1b078c9b 100644 --- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c +++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c @@ -1623,12 +1623,7 @@ static const uint32_t TermcodeBySample[20][3] = { #define PFC_PUD6 0xE6060458U #define GPIO_INDT5 0xE605500CU #define GPIO_INDT6 0xE605540CU - -#define BIT25 BIT(25) -#define BIT22 BIT(22) -#define BIT15 BIT(15) -#define BIT0 BIT(0) -#define GPIO_GPSR6 (0xE6060118U) +#define GPIO_GPSR6 0xE6060118U #if (RCAR_GEN3_ULCB == 0) static void pfc_write_and_poll(uint32_t a, uint32_t v) @@ -1659,17 +1654,17 @@ static uint32_t opencheck_SSI_WS6(void) pud5_bak = mmio_read_32(PFC_PUD5); dsb_sev(); - dataL = (gpsr6_bak & ~BIT15); + dataL = (gpsr6_bak & ~BIT(15)); pfc_write_and_poll(GPIO_GPSR6, dataL); /* Pull-Up/Down Enable (PUEN5[22]=1) */ dataL = puen5_bak; - dataL |= (BIT22); + dataL |= (BIT(22)); pfc_write_and_poll(PFC_PUEN5, dataL); /* Pull-Down-Enable (PUD5[22]=0, PUEN5[22]=1) */ dataL = pud5_bak; - dataL &= ~(BIT22); + dataL &= ~(BIT(22)); pfc_write_and_poll(PFC_PUD5, dataL); /* GPSR6[15]=SSI_WS6 */ rcar_micro_delay(10); @@ -1678,7 +1673,7 @@ static uint32_t opencheck_SSI_WS6(void) /* Pull-Up-Enable (PUD5[22]=1, PUEN5[22]=1) */ dataL = pud5_bak; - dataL |= (BIT22); + dataL |= (BIT(22)); pfc_write_and_poll(PFC_PUD5, dataL); /* GPSR6[15]=SSI_WS6 */ diff --git a/include/arch/aarch32/console_macros.S b/include/arch/aarch32/console_macros.S index 070be849de..996cb327f3 100644 --- a/include/arch/aarch32/console_macros.S +++ b/include/arch/aarch32/console_macros.S @@ -15,7 +15,7 @@ * default consoles are enabled for the "boot" and "crash" states, this can be * changed after registration with the console_set_scope() function). It ends * with a tail call that will include return to the caller. - * REQUIRES console_t pointer in x0 and a valid return address in x30. + * REQUIRES console_t pointer in r0 and a valid return address in lr. */ .macro finish_console_register _driver, putc=0, getc=0, flush=0 /* |