diff options
-rw-r--r-- | bl1/aarch64/bl1_arch_setup.c | 3 | ||||
-rw-r--r-- | bl1/aarch64/bl1_entrypoint.S | 10 | ||||
-rw-r--r-- | bl31/aarch64/bl31_arch_setup.c | 3 |
3 files changed, 12 insertions, 4 deletions
diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c index 758b8e8feb..1b14246b70 100644 --- a/bl1/aarch64/bl1_arch_setup.c +++ b/bl1/aarch64/bl1_arch_setup.c @@ -39,10 +39,9 @@ void bl1_arch_setup(void) { unsigned long tmp_reg = 0; - /* Enable alignment checks and set the exception endianess to LE */ + /* Enable alignment checks */ tmp_reg = read_sctlr_el3(); tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT); - tmp_reg &= ~SCTLR_EE_BIT; write_sctlr_el3(tmp_reg); /* diff --git a/bl1/aarch64/bl1_entrypoint.S b/bl1/aarch64/bl1_entrypoint.S index 012b779c77..62e12181da 100644 --- a/bl1/aarch64/bl1_entrypoint.S +++ b/bl1/aarch64/bl1_entrypoint.S @@ -43,6 +43,16 @@ func bl1_entrypoint /* --------------------------------------------- + * Set the CPU endianness before doing anything + * that might involve memory reads or writes + * --------------------------------------------- + */ + mrs x0, sctlr_el3 + bic x0, x0, #SCTLR_EE_BIT + msr sctlr_el3, x0 + isb + + /* --------------------------------------------- * Perform any processor specific actions upon * reset e.g. cache, tlb invalidations etc. * --------------------------------------------- diff --git a/bl31/aarch64/bl31_arch_setup.c b/bl31/aarch64/bl31_arch_setup.c index acaa6b5710..ad73de022e 100644 --- a/bl31/aarch64/bl31_arch_setup.c +++ b/bl31/aarch64/bl31_arch_setup.c @@ -45,10 +45,9 @@ void bl31_arch_setup(void) unsigned long tmp_reg = 0; uint64_t counter_freq; - /* Enable alignment checks and set the exception endianness to LE */ + /* Enable alignment checks */ tmp_reg = read_sctlr_el3(); tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT); - tmp_reg &= ~SCTLR_EE_BIT; write_sctlr_el3(tmp_reg); /* |