diff options
-rw-r--r-- | Makefile | 8 | ||||
-rw-r--r-- | drivers/arm/gic/v2/gicv2_main.c | 16 | ||||
-rw-r--r-- | include/drivers/marvell/cache_llc.h | 4 | ||||
-rw-r--r-- | plat/brcm/board/stingray/src/brcm_pm_ops.c | 2 | ||||
-rw-r--r-- | plat/nvidia/tegra/include/drivers/memctrl_v2.h | 8 | ||||
-rw-r--r-- | plat/nvidia/tegra/include/t186/tegra_mc_def.h | 4 |
6 files changed, 18 insertions, 24 deletions
@@ -1067,14 +1067,6 @@ ifneq ($(findstring clang,$(notdir $(CC))),) else CPPFLAGS += -Wno-error=deprecated-declarations -Wno-error=cpp endif -# __ASSEMBLY__ is deprecated in favor of the compiler-builtin __ASSEMBLER__. -ASFLAGS += -D__ASSEMBLY__ -# AARCH32/AARCH64 macros are deprecated in favor of the compiler-builtin __aarch64__. -ifeq (${ARCH},aarch32) - $(eval $(call add_define,AARCH32)) -else - $(eval $(call add_define,AARCH64)) -endif endif # !ERROR_DEPRECATED $(eval $(call MAKE_LIB_DIRS)) diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c index 4b21b920a7..939d097188 100644 --- a/drivers/arm/gic/v2/gicv2_main.c +++ b/drivers/arm/gic/v2/gicv2_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -296,8 +296,8 @@ void gicv2_set_pe_target_mask(unsigned int proc_num) assert(driver_data != NULL); assert(driver_data->gicd_base != 0U); assert(driver_data->target_masks != NULL); - assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE); - assert((unsigned int)proc_num < driver_data->target_masks_num); + assert(proc_num < GICV2_MAX_TARGET_PE); + assert(proc_num < driver_data->target_masks_num); /* Return if the target mask is already populated */ if (driver_data->target_masks[proc_num] != 0U) @@ -422,7 +422,8 @@ void gicv2_raise_sgi(int sgi_num, int proc_num) unsigned int sgir_val, target; assert(driver_data != NULL); - assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE); + assert(proc_num >= 0); + assert(proc_num < (int)GICV2_MAX_TARGET_PE); assert(driver_data->gicd_base != 0U); /* @@ -430,7 +431,7 @@ void gicv2_raise_sgi(int sgi_num, int proc_num) * should be valid. */ assert(driver_data->target_masks != NULL); - assert((unsigned int)proc_num < driver_data->target_masks_num); + assert(proc_num < (int)driver_data->target_masks_num); /* Don't raise SGI if the mask hasn't been populated */ target = driver_data->target_masks[proc_num]; @@ -466,8 +467,9 @@ void gicv2_set_spi_routing(unsigned int id, int proc_num) * should be valid. */ assert(driver_data->target_masks != NULL); - assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE); - assert((unsigned int)proc_num < driver_data->target_masks_num); + assert(proc_num < (int)GICV2_MAX_TARGET_PE); + assert(driver_data->target_masks_num < INT_MAX); + assert(proc_num < (int)driver_data->target_masks_num); if (proc_num < 0) { /* Target all PEs */ diff --git a/include/drivers/marvell/cache_llc.h b/include/drivers/marvell/cache_llc.h index d6dd65382f..72111b374a 100644 --- a/include/drivers/marvell/cache_llc.h +++ b/include/drivers/marvell/cache_llc.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018 Marvell International Ltd. + * Copyright (C) 2018-2020 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -57,6 +57,6 @@ int llc_sram_enable(int ap_index, int size); void llc_sram_disable(int ap_index); int llc_sram_test(int ap_index, int size, char *msg); #endif /* LLC_SRAM */ -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* CACHE_LLC_H */ diff --git a/plat/brcm/board/stingray/src/brcm_pm_ops.c b/plat/brcm/board/stingray/src/brcm_pm_ops.c index 090fbca538..03a604c152 100644 --- a/plat/brcm/board/stingray/src/brcm_pm_ops.c +++ b/plat/brcm/board/stingray/src/brcm_pm_ops.c @@ -323,7 +323,7 @@ static int brcm_validate_ns_entrypoint(uintptr_t entrypoint) if ((entrypoint >= BRCM_NS_DRAM1_BASE) && (entrypoint < (BRCM_NS_DRAM1_BASE + BRCM_NS_DRAM1_SIZE))) return PSCI_E_SUCCESS; -#ifndef AARCH32 +#ifdef __aarch64__ if ((entrypoint >= BRCM_DRAM2_BASE) && (entrypoint < (BRCM_DRAM2_BASE + BRCM_DRAM2_SIZE))) return PSCI_E_SUCCESS; diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v2.h b/plat/nvidia/tegra/include/drivers/memctrl_v2.h index 1e153063a6..9af3027ea3 100644 --- a/plat/nvidia/tegra/include/drivers/memctrl_v2.h +++ b/plat/nvidia/tegra/include/drivers/memctrl_v2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -26,7 +26,7 @@ #define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \ MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <assert.h> @@ -53,9 +53,9 @@ typedef struct mc_regs { .val = 0xFFFFFFFFU, \ } -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <lib/mmio.h> diff --git a/plat/nvidia/tegra/include/t186/tegra_mc_def.h b/plat/nvidia/tegra/include/t186/tegra_mc_def.h index 398453eb95..fa447725ba 100644 --- a/plat/nvidia/tegra/include/t186/tegra_mc_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_mc_def.h @@ -282,7 +282,7 @@ #define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1U << 24) #define MC_CLIENT_HOTRESET_STATUS1 0x974U -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ /******************************************************************************* * Structure to hold the transaction override settings to use to override @@ -393,6 +393,6 @@ typedef struct mc_streamid_security_cfg { MC_TXN_OVERRIDE_CONFIG_CGID_##so_dev_axi_id); \ } while (0) -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* TEGRA_MC_DEF_H */ |