diff options
148 files changed, 1538 insertions, 830 deletions
@@ -865,6 +865,7 @@ $(eval $(call assert_booleans,\ CTX_INCLUDE_PAUTH_REGS \ CTX_INCLUDE_MTE_REGS \ CTX_INCLUDE_EL2_REGS \ + CTX_INCLUDE_NEVE_REGS \ DEBUG \ DYN_DISABLE_AUTH \ EL3_EXCEPTION_HANDLING \ @@ -953,6 +954,7 @@ $(eval $(call add_defines,\ EL3_EXCEPTION_HANDLING \ CTX_INCLUDE_MTE_REGS \ CTX_INCLUDE_EL2_REGS \ + CTX_INCLUDE_NEVE_REGS \ DECRYPTION_SUPPORT_${DECRYPTION_SUPPORT} \ ENABLE_AMU \ ENABLE_ASSERTIONS \ @@ -1067,14 +1069,6 @@ ifneq ($(findstring clang,$(notdir $(CC))),) else CPPFLAGS += -Wno-error=deprecated-declarations -Wno-error=cpp endif -# __ASSEMBLY__ is deprecated in favor of the compiler-builtin __ASSEMBLER__. -ASFLAGS += -D__ASSEMBLY__ -# AARCH32/AARCH64 macros are deprecated in favor of the compiler-builtin __aarch64__. -ifeq (${ARCH},aarch32) - $(eval $(call add_define,AARCH32)) -else - $(eval $(call add_define,AARCH64)) -endif endif # !ERROR_DEPRECATED $(eval $(call MAKE_LIB_DIRS)) diff --git a/bl1/aarch64/bl1_context_mgmt.c b/bl1/aarch64/bl1_context_mgmt.c index 87e367ce81..2a8d58efd1 100644 --- a/bl1/aarch64/bl1_context_mgmt.c +++ b/bl1/aarch64/bl1_context_mgmt.c @@ -78,8 +78,8 @@ void bl1_prepare_next_image(unsigned int image_id) mode = MODE_EL2; } - next_bl_ep->spsr = (uint32_t)SPSR_64(mode, MODE_SP_ELX, - DISABLE_ALL_EXCEPTIONS); + next_bl_ep->spsr = (uint32_t)SPSR_64((uint64_t) mode, + (uint64_t)MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); /* Allow platform to make change */ bl1_plat_set_ep_info(image_id, next_bl_ep); diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index 5026500979..8a1573ab61 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -37,7 +37,7 @@ SECTIONS .text . : { __TEXT_START__ = .; *bl31_entrypoint.o(.text*) - *(SORT_BY_ALIGNMENT(.text*)) + *(SORT_BY_ALIGNMENT(SORT(.text*))) *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; diff --git a/bl32/sp_min/sp_min.ld.S b/bl32/sp_min/sp_min.ld.S index 9e0596f1f0..f202c7ada8 100644 --- a/bl32/sp_min/sp_min.ld.S +++ b/bl32/sp_min/sp_min.ld.S @@ -22,14 +22,14 @@ MEMORY { SECTIONS { . = BL32_BASE; - ASSERT(. == ALIGN(PAGE_SIZE), - "BL32_BASE address is not aligned on a page boundary.") + ASSERT(. == ALIGN(PAGE_SIZE), + "BL32_BASE address is not aligned on a page boundary.") #if SEPARATE_CODE_AND_RODATA .text . : { __TEXT_START__ = .; *entrypoint.o(.text*) - *(.text*) + *(SORT_BY_ALIGNMENT(.text*)) *(.vectors) . = ALIGN(PAGE_SIZE); __TEXT_END__ = .; @@ -46,7 +46,7 @@ SECTIONS .rodata . : { __RODATA_START__ = .; - *(.rodata*) + *(SORT_BY_ALIGNMENT(.rodata*)) RODATA_COMMON @@ -61,8 +61,8 @@ SECTIONS ro . : { __RO_START__ = .; *entrypoint.o(.text*) - *(.text*) - *(.rodata*) + *(SORT_BY_ALIGNMENT(.text*)) + *(SORT_BY_ALIGNMENT(.rodata*)) RODATA_COMMON @@ -76,7 +76,7 @@ SECTIONS /* * Memory page(s) mapped to this section will be marked as * read-only, executable. No RW data from the next section must - * creep in. Ensure the rest of the current memory block is unused. + * creep in. Ensure the rest of the current memory page is unused. */ . = ALIGN(PAGE_SIZE); __RO_END__ = .; @@ -134,10 +134,12 @@ SECTIONS #endif /* - * Define a linker symbol to mark end of the RW memory area for this + * Define a linker symbol to mark the end of the RW memory area for this * image. */ __RW_END__ = .; - __BL32_END__ = .; + __BL32_END__ = .; + + ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.") } diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index ebc5c2c3d4..a007bab302 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -60,7 +60,7 @@ func tsp_entrypoint _align=3 */ pie_fixup: ldr x0, =pie_fixup - and x0, x0, #~(PAGE_SIZE - 1) + and x0, x0, #~(PAGE_SIZE_MASK) mov_imm x1, (BL32_LIMIT - BL32_BASE) add x1, x1, x0 bl fixup_gdt_reloc diff --git a/common/backtrace/backtrace.c b/common/backtrace/backtrace.c index a07c066cea..25e2c707b7 100644 --- a/common/backtrace/backtrace.c +++ b/common/backtrace/backtrace.c @@ -261,7 +261,7 @@ void backtrace(const char *cookie) struct frame_record *fr = __builtin_frame_address(0U); /* Printing the backtrace may crash the system, flush before starting */ - (void)console_flush(); + console_flush(); fr = adjust_frame_record(fr); diff --git a/common/bl_common.c b/common/bl_common.c index 2fcb5385d9..f17afcb115 100644 --- a/common/bl_common.c +++ b/common/bl_common.c @@ -50,8 +50,8 @@ static int dyn_is_auth_disabled(void) uintptr_t page_align(uintptr_t value, unsigned dir) { /* Round up the limit to the next page boundary */ - if ((value & (PAGE_SIZE - 1U)) != 0U) { - value &= ~(PAGE_SIZE - 1U); + if ((value & PAGE_SIZE_MASK) != 0U) { + value &= ~PAGE_SIZE_MASK; if (dir == UP) value += PAGE_SIZE; } diff --git a/common/fdt_fixup.c b/common/fdt_fixup.c index a1604e74f7..e88a550080 100644 --- a/common/fdt_fixup.c +++ b/common/fdt_fixup.c @@ -425,7 +425,8 @@ int fdt_adjust_gic_redist(void *dtb, unsigned int nr_cores, redist_size_32 = cpu_to_fdt32(nr_cores * gicr_frame_size); val = &redist_size_32; } else { - redist_size_64 = cpu_to_fdt64(nr_cores * gicr_frame_size); + redist_size_64 = cpu_to_fdt64(nr_cores * + (uint64_t)gicr_frame_size); val = &redist_size_64; } diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst index f3167fb256..55c8bdaf43 100644 --- a/docs/about/release-information.rst +++ b/docs/about/release-information.rst @@ -42,7 +42,9 @@ depending on project requirement and partner feedback. +-----------------+---------------------------+------------------------------+ | v2.3 | 4th week of Apr '20 | 1st week of Apr '20 | +-----------------+---------------------------+------------------------------+ -| v2.4 | 4th week of Oct '20 | 1st week of Oct '20 | +| v2.4 | 2nd week of Nov '20 | 4th week of Oct '20 | ++-----------------+---------------------------+------------------------------+ +| v2.5 | 2nd week of May '21 | 4th week of Apr '21 | +-----------------+---------------------------+------------------------------+ Removal of Deprecated Interfaces @@ -57,9 +59,7 @@ Release version after which it will be removed. | | Date | after | | | | | Release | | +================================+=============+=========+=========================================================+ -| ``AARCH32``/``AARCH64`` macros | Oct '19 | v2.3 | Deprecated in favor of ``__aarch64__`` | -+--------------------------------+-------------+---------+---------------------------------------------------------+ -| ``__ASSEMBLY__`` macro | Oct '19 | v2.3 | Deprecated in favor of ``__ASSEMBLER__`` | +| | | | | +--------------------------------+-------------+---------+---------------------------------------------------------+ -------------- diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 8152c00d58..c976b8b3a9 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -260,6 +260,9 @@ For Cortex-A77, the following errata build flags are defined : - ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77 CPU. This needs to be enabled only for revision <= r1p1 of the CPU. +- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77 + CPU. This needs to be enabled only for revision <= r1p1 of the CPU. + For Cortex-A78, the following errata build flags are defined : - ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst index 40fc5dbbc9..8adf4ad8ba 100644 --- a/docs/getting_started/build-options.rst +++ b/docs/getting_started/build-options.rst @@ -161,6 +161,10 @@ Common build options registers to be included when saving and restoring the CPU context. Default is 0. +- ``CTX_INCLUDE_NEVE_REGS``: Boolean option that, when set to 1, will cause the + Armv8.4-NV registers to be saved/restored when entering/exiting an EL2 + execution context. Default value is 0. + - ``CTX_INCLUDE_PAUTH_REGS``: Boolean option that, when set to 1, enables Pointer Authentication for Secure world. This will cause the ARMv8.3-PAuth registers to be included when saving and restoring the CPU context as diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst index f3316164bb..19e26e4ea1 100644 --- a/docs/getting_started/porting-guide.rst +++ b/docs/getting_started/porting-guide.rst @@ -2724,12 +2724,11 @@ Function : plat_crash_console_flush [mandatory] :: Argument : void - Return : int + Return : void This API is used by the crash reporting mechanism to force write of all buffered data on the designated crash console. It should only use general purpose -registers x0 through x5 to do its work. The return value is 0 on successful -completion; otherwise the return value is -1. +registers x0 through x5 to do its work. .. _External Abort handling and RAS Support: diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst index e3bf42ad9d..3a13268fa3 100644 --- a/docs/plat/arm/fvp/index.rst +++ b/docs/plat/arm/fvp/index.rst @@ -12,8 +12,9 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores (64-bit host machine only). .. note:: - The FVP models used are Version 11.9 Build 41, unless otherwise stated. + The FVP models used are Version 11.12 Build 38, unless otherwise stated. +- ``FVP_Base_AEMvA`` - ``FVP_Base_AEMv8A-AEMv8A`` - ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` - ``FVP_Base_RevC-2xAEMv8A`` @@ -37,22 +38,26 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores - ``FVP_Base_Cortex-A76AEx4`` - ``FVP_Base_Cortex-A76AEx8`` - ``FVP_Base_Cortex-A77x4`` +- ``FVP_Base_Cortex-A78x4`` - ``FVP_Base_Neoverse-E1x1`` - ``FVP_Base_Neoverse-E1x2`` - ``FVP_Base_Neoverse-E1x4`` - ``FVP_Base_Neoverse-N1x4`` -- ``FVP_Base_Zeusx4`` +- ``FVP_Base_Neoverse-V1x4`` - ``FVP_CSS_SGI-575`` (Version 11.10 build 36) - ``FVP_CSS_SGM-775`` -- ``FVP_RD_E1_edge`` (Version 11.10 build 36) +- ``FVP_RD_E1_edge`` (Version 11.9 build 41) - ``FVP_RD_N1_edge`` (Version 11.10 build 36) - ``FVP_RD_N1_edge_dual`` (Version 11.10 build 36) +- ``FVP_RD_Daniel`` (Version 11.10 build 36) +- ``FVP_TC0`` (Version 0.0 build 6114) - ``Foundation_Platform`` The latest version of the AArch32 build of TF-A has been tested on the following Arm FVPs without shifted affinities, and that do not support threaded CPU cores (64-bit host machine only). +- ``FVP_Base_AEMvA`` - ``FVP_Base_AEMv8A-AEMv8A`` - ``FVP_Base_Cortex-A32x4`` diff --git a/docs/plat/stm32mp1.rst b/docs/plat/stm32mp1.rst index 263867c25e..f597460db2 100644 --- a/docs/plat/stm32mp1.rst +++ b/docs/plat/stm32mp1.rst @@ -8,6 +8,23 @@ The STM32MP1 chip also embeds a Cortex-M4. More information can be found on `STM32MP1 Series`_ page. +STM32MP1 Versions +----------------- +The STM32MP1 series is available in 3 different lines which are pin-to-pin compatible: + +- STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD +- STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD +- STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz + +Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option: + +- A Basic + Cortex-A7 @ 650 MHz +- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz +- D Basic + Cortex-A7 @ 800 MHz +- F Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz + +The `STM32MP1 part number codification`_ page gives more information about part numbers. + Design ------ The STM32MP1 resets in the ROM code of the Cortex-A7. @@ -129,3 +146,4 @@ OP-TEE artifacts go into separate partitions as follows: .. _STM32MP1 Series: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html +.. _STM32MP1 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP15_microprocessor#Part_number_codification diff --git a/docs/process/code-review-guidelines.rst b/docs/process/code-review-guidelines.rst new file mode 100644 index 0000000000..67a211f753 --- /dev/null +++ b/docs/process/code-review-guidelines.rst @@ -0,0 +1,216 @@ +Code Review Guidelines +====================== + +This document provides TF-A specific details about the project's code review +process. It should be read in conjunction with the `Project Maintenance +Process`_, which it supplements. + + +Why do we do code reviews? +-------------------------- + +The main goal of code reviews is to improve the code quality. By reviewing each +other's code, we can help catch issues that were missed by the author +before they are integrated in the source tree. Different people bring different +perspectives, depending on their past work, experiences and their current use +cases of TF-A in their products. + +Code reviews also play a key role in sharing knowledge within the +community. People with more expertise in one area of the code base can +help those that are less familiar with it. + +Code reviews are meant to benefit everyone through team work. It is not about +unfairly criticizing or belittling the work of any contributor. + + +Good practices +-------------- + +To ensure the code review gives the greatest possible benefit, participants in +the project should: + +- Be considerate of other people and their needs. Participants may be working + to different timescales, and have different priorities. Keep this in + mind - be gracious while waiting for action from others, and timely in your + actions when others are waiting for you. + +- Review other people's patches where possible. The more active reviewers there + are, the more quickly new patches can be reviewed and merged. Contributing to + code review helps everyone in the long run, as it creates a culture of + participation which serves everyone's interests. + + +Guidelines for patch contributors +--------------------------------- + +In addition to the rules outlined in the :ref:`Contributor's Guide`, as a patch +contributor you are expected to: + +- Answer all comments from people who took the time to review your + patches. + +- Be patient and resilient. It is quite common for patches to go through + several rounds of reviews and rework before they get approved, especially + for larger features. + + In the event that a code review takes longer than you would hope for, you + may try the following actions to speed it up: + + - Ping the reviewers on Gerrit or on the mailing list. If it is urgent, + explain why. Please remain courteous and do not abuse this. + + - If one code owner has become unresponsive, ask the other code owners for + help progressing the patch. + + - If there is only one code owner and they have become unresponsive, ask one + of the project maintainers for help. + +- Do the right thing for the project, not the fastest thing to get code merged. + + For example, if some existing piece of code - say a driver - does not quite + meet your exact needs, go the extra mile and extend the code with the missing + functionality you require - as opposed to copying the code into some other + directory to have the freedom to change it in any way. This way, your changes + benefit everyone and will be maintained over time. + + +Guidelines for all reviewers +---------------------------- + +There are no good or bad review comments. If you have any doubt about a patch or +need some clarifications, it's better to ask rather than letting a potential +issue slip. Examples of review comments could be: + +- Questions ("Why do you need to do this?", "What if X happens?") +- Bugs ("I think you need a logical \|\| rather than a bitwise \|.") +- Design issues ("This won't scale well when we introduce feature X.") +- Improvements ("Would it be better if we did Y instead?") + + +Guidelines for code owners +-------------------------- + +Code owners are listed on the :ref:`Project Maintenance<code owners>` page, +along with the module(s) they look after. + +When reviewing a patch, code owners are expected to check the following: + +- The patch looks good from a technical point of view. For example: + + - The structure of the code is clear. + + - It complies with the relevant standards or technical documentation (where + applicable). + + - It leverages existing interfaces rather than introducing new ones + unnecessarily. + + - It fits well in the design of the module. + + - It adheres to the security model of the project. In particular, it does not + increase the attack surface (e.g. new SMCs) without justification. + +- The patch adheres to the TF-A :ref:`Coding Style`. The CI system should help + catch coding style violations. + +- (Only applicable to generic code) The code is MISRA-compliant (see + :ref:`misra-compliance`). The CI system should help catch violations. + +- Documentation is provided/updated (where applicable). + +- The patch has had an appropriate level of testing. Testing details are + expected to be provided by the patch author. If they are not, do not hesitate + to request this information. + +- All CI automated tests pass. + +If a code owner is happy with a patch, they should give their approval +through the ``Code-Owner-Review+1`` label in Gerrit. If instead, they have +concerns, questions, or any other type of blocking comment, they should set +``Code-Owner-Review-1``. + +Code owners are expected to behave professionally and responsibly. Here are some +guidelines for them: + +- Once you are engaged in a review, make sure you stay involved until the patch + is merged. Rejecting a patch and going away is not very helpful. You are + expected to monitor the patch author's answers to your review comments, + answer back if needed and review new revisions of their patch. + +- Provide constructive feedback. Just saying, "This is wrong, you should do X + instead." is usually not very helpful. The patch author is unlikely to + understand why you are requesting this change and might feel personally + attacked. + +- Be mindful when reviewing a patch. As a code owner, you are viewed as + the expert for the relevant module. By approving a patch, you are partially + responsible for its quality and the effects it has for all TF-A users. Make + sure you fully understand what the implications of a patch might be. + + +Guidelines for maintainers +-------------------------- + +Maintainers are listed on the :ref:`Project Maintenance<maintainers>` page. + +When reviewing a patch, maintainers are expected to check the following: + +- The general structure of the patch looks good. This covers things like: + + - Code organization. + + - Files and directories, names and locations. + + For example, platform code should be added under the ``plat/`` directory. + + - Naming conventions. + + For example, platform identifiers should be properly namespaced to avoid + name clashes with generic code. + + - API design. + +- Interaction of the patch with other modules in the code base. + +- The patch aims at complying with any standard or technical documentation + that applies. + +- New files must have the correct license and copyright headers. See :ref:`this + paragraph<copyright-license-guidance>` for more information. The CI system + should help catch files with incorrect or no copyright/license headers. + +- There is no third party code or binary blobs with potential IP concerns. + Maintainers should look for copyright or license notices in code, and use + their best judgement. If they are unsure about a patch, they should ask + other maintainers for help. + +- Generally speaking, new driver code should be placed in the generic + layer. There are cases where a driver has to stay into the platform layer but + this should be the exception, rather than the rule. + +- Existing common drivers (in particular for Arm IPs like the GIC driver) should + not be copied into the platform layer to cater for platform quirks. This + type of code duplication hurts the maintainability of the project. The + duplicate driver is less likely to benefit from bug fixes and future + enhancements. In most cases, it is possible to rework a generic driver to + make it more flexible and fit slightly different use cases. That way, these + enhancements benefit everyone. + +- When a platform specific driver really is required, the burden lies with the + patch author to prove the need for it. A detailed justification should be + posted via the commit message or on the mailing list. + +- Before merging a patch, verify that all review comments have been addressed. + If this is not the case, encourage the patch author and the relevant + reviewers to resolve these together. + +If a maintainer is happy with a patch, they should give their approval +through the ``Maintainer-Review+1`` label in Gerrit. If instead, they have +concerns, questions, or any other type of blocking comment, they should set +``Maintainer-Review-1``. + +-------------- + +*Copyright (c) 2020, Arm Limited. All rights reserved.* + +.. _Project Maintenance Process: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/ diff --git a/docs/process/coding-style.rst b/docs/process/coding-style.rst index fd1984d303..94fd85e363 100644 --- a/docs/process/coding-style.rst +++ b/docs/process/coding-style.rst @@ -42,6 +42,8 @@ Both GCC and Clang compiler toolchains have support for *GNU99* mode, though Clang does lack support for a small number of GNU extensions. These missing extensions are rarely used, however, and should not pose a problem. +.. _misra-compliance: + MISRA Compliance ---------------- diff --git a/docs/process/contributing.rst b/docs/process/contributing.rst index 0b3b848f42..15c2b4529a 100644 --- a/docs/process/contributing.rst +++ b/docs/process/contributing.rst @@ -90,6 +90,8 @@ Making Changes (and nothing else) in the last commit of the series. Otherwise, include the documentation changes within the single commit. +.. _copyright-license-guidance: + - Ensure that each changed file has the correct copyright and license information. Files that entirely consist of contributions to this project should have a copyright notice and BSD-3-Clause SPDX license identifier of diff --git a/docs/process/index.rst b/docs/process/index.rst index 1cb5354056..37324b0e9f 100644 --- a/docs/process/index.rst +++ b/docs/process/index.rst @@ -11,5 +11,6 @@ Processes & Policies coding-style coding-guidelines contributing + code-review-guidelines faq security-hardening diff --git a/drivers/amlogic/console/aarch64/meson_console.S b/drivers/amlogic/console/aarch64/meson_console.S index 39c2545e73..6d0a2d62e7 100644 --- a/drivers/amlogic/console/aarch64/meson_console.S +++ b/drivers/amlogic/console/aarch64/meson_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -224,11 +224,11 @@ func console_meson_core_getc endfunc console_meson_core_getc /* --------------------------------------------- - * int console_meson_flush(console_t *console) + * void console_meson_flush(console_t *console) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - pointer to console_t structure - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : x0, x1 * --------------------------------------------- */ @@ -242,11 +242,11 @@ func console_meson_flush endfunc console_meson_flush /* --------------------------------------------- - * int console_meson_core_flush(uintptr_t base_addr) + * void console_meson_core_flush(uintptr_t base_addr) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - console base address - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : x0, x1 * --------------------------------------------- */ @@ -258,6 +258,5 @@ func console_meson_core_flush /* Wait until the transmit FIFO is empty */ 1: ldr w1, [x0, #MESON_STATUS_OFFSET] tbz w1, #MESON_STATUS_TX_EMPTY_BIT, 1b - mov w0, #0 ret endfunc console_meson_core_flush diff --git a/drivers/arm/cci/cci.c b/drivers/arm/cci/cci.c index a139f6cc74..2adfe1718b 100644 --- a/drivers/arm/cci/cci.c +++ b/drivers/arm/cci/cci.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -52,11 +52,11 @@ static bool validate_cci_map(const int *map) return false; } - if ((valid_cci_map & (1U << slave_if_id)) != 0U) { + if ((valid_cci_map & (1UL << slave_if_id)) != 0U) { ERROR("Multiple masters are assigned same slave interface ID\n"); return false; } - valid_cci_map |= 1U << slave_if_id; + valid_cci_map |= 1UL << slave_if_id; } if (valid_cci_map == 0U) { diff --git a/drivers/arm/gic/v2/gicv2_main.c b/drivers/arm/gic/v2/gicv2_main.c index 4b21b920a7..939d097188 100644 --- a/drivers/arm/gic/v2/gicv2_main.c +++ b/drivers/arm/gic/v2/gicv2_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -296,8 +296,8 @@ void gicv2_set_pe_target_mask(unsigned int proc_num) assert(driver_data != NULL); assert(driver_data->gicd_base != 0U); assert(driver_data->target_masks != NULL); - assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE); - assert((unsigned int)proc_num < driver_data->target_masks_num); + assert(proc_num < GICV2_MAX_TARGET_PE); + assert(proc_num < driver_data->target_masks_num); /* Return if the target mask is already populated */ if (driver_data->target_masks[proc_num] != 0U) @@ -422,7 +422,8 @@ void gicv2_raise_sgi(int sgi_num, int proc_num) unsigned int sgir_val, target; assert(driver_data != NULL); - assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE); + assert(proc_num >= 0); + assert(proc_num < (int)GICV2_MAX_TARGET_PE); assert(driver_data->gicd_base != 0U); /* @@ -430,7 +431,7 @@ void gicv2_raise_sgi(int sgi_num, int proc_num) * should be valid. */ assert(driver_data->target_masks != NULL); - assert((unsigned int)proc_num < driver_data->target_masks_num); + assert(proc_num < (int)driver_data->target_masks_num); /* Don't raise SGI if the mask hasn't been populated */ target = driver_data->target_masks[proc_num]; @@ -466,8 +467,9 @@ void gicv2_set_spi_routing(unsigned int id, int proc_num) * should be valid. */ assert(driver_data->target_masks != NULL); - assert((unsigned int)proc_num < GICV2_MAX_TARGET_PE); - assert((unsigned int)proc_num < driver_data->target_masks_num); + assert(proc_num < (int)GICV2_MAX_TARGET_PE); + assert(driver_data->target_masks_num < INT_MAX); + assert(proc_num < (int)driver_data->target_masks_num); if (proc_num < 0) { /* Target all PEs */ diff --git a/drivers/arm/pl011/aarch32/pl011_console.S b/drivers/arm/pl011/aarch32/pl011_console.S index 93045f03dc..9caeb0c692 100644 --- a/drivers/arm/pl011/aarch32/pl011_console.S +++ b/drivers/arm/pl011/aarch32/pl011_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -222,17 +222,19 @@ func console_pl011_getc endfunc console_pl011_getc /* --------------------------------------------- - * int console_core_flush(uintptr_t base_addr) + * void console_core_flush(uintptr_t base_addr) * Function to force a write of all buffered * data that hasn't been output. * In : r0 - console base address - * Out : return -1 on error else return 0. + * Out : void * Clobber list : r0, r1 * --------------------------------------------- */ func console_pl011_core_flush +#if ENABLE_ASSERTIONS cmp r0, #0 - beq flush_error + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ 1: /* Loop while the transmit FIFO is busy */ @@ -240,19 +242,15 @@ func console_pl011_core_flush tst r1, #PL011_UARTFR_BUSY bne 1b - mov r0, #0 - bx lr -flush_error: - mov r0, #-1 bx lr endfunc console_pl011_core_flush /* --------------------------------------------- - * int console_pl011_flush(console_t *console) + * void console_pl011_flush(console_t *console) * Function to force a write of all buffered * data that hasn't been output. * In : r0 - pointer to console_t structure - * Out : return -1 on error else return 0. + * Out : void * Clobber list: r0, r1 * --------------------------------------------- */ diff --git a/drivers/arm/pl011/aarch64/pl011_console.S b/drivers/arm/pl011/aarch64/pl011_console.S index 3a2a3cdb43..861d2ed22d 100644 --- a/drivers/arm/pl011/aarch64/pl011_console.S +++ b/drivers/arm/pl011/aarch64/pl011_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -208,11 +208,11 @@ func console_pl011_getc endfunc console_pl011_getc /* --------------------------------------------- - * int console_pl011_core_flush(uintptr_t base_addr) + * void console_pl011_core_flush(uintptr_t base_addr) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - console base address - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : x0, x1 * --------------------------------------------- */ @@ -225,17 +225,15 @@ func console_pl011_core_flush /* Loop until the transmit FIFO is empty */ ldr w1, [x0, #UARTFR] tbnz w1, #PL011_UARTFR_BUSY_BIT, 1b - - mov w0, #0 ret endfunc console_pl011_core_flush /* --------------------------------------------- - * int console_pl011_flush(console_t *console) + * void console_pl011_flush(console_t *console) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - pointer to console_t structure - * Out : return -1 on error else return 0. + * Out : void * Clobber list : x0, x1 * --------------------------------------------- */ diff --git a/drivers/arm/tzc/tzc400.c b/drivers/arm/tzc/tzc400.c index 50d6701398..95a5e7f77f 100644 --- a/drivers/arm/tzc/tzc400.c +++ b/drivers/arm/tzc/tzc400.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -91,9 +91,9 @@ static void _tzc400_set_gate_keeper(uintptr_t base, open_status = get_gate_keeper_os(base); if (val != 0) - open_status |= (1U << filter); + open_status |= (1UL << filter); else - open_status &= ~(1U << filter); + open_status &= ~(1UL << filter); _tzc400_write_gate_keeper(base, (open_status & GATE_KEEPER_OR_MASK) << GATE_KEEPER_OR_SHIFT); diff --git a/drivers/arm/tzc/tzc_common_private.h b/drivers/arm/tzc/tzc_common_private.h index c800536f33..1d99077ad1 100644 --- a/drivers/arm/tzc/tzc_common_private.h +++ b/drivers/arm/tzc/tzc_common_private.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -30,13 +30,13 @@ mmio_write_32(base + \ TZC_REGION_OFFSET( \ TZC_##macro_name##_REGION_SIZE, \ - region_no) + \ + (u_register_t)region_no) + \ TZC_##macro_name##_REGION_BASE_LOW_0_OFFSET, \ (uint32_t)region_base); \ mmio_write_32(base + \ TZC_REGION_OFFSET( \ TZC_##macro_name##_REGION_SIZE, \ - region_no) + \ + (u_register_t)region_no) + \ TZC_##macro_name##_REGION_BASE_HIGH_0_OFFSET, \ (uint32_t)(region_base >> 32)); \ } @@ -48,15 +48,15 @@ unsigned long long region_top) \ { \ mmio_write_32(base + \ - TZC_REGION_OFFSET \ - (TZC_##macro_name##_REGION_SIZE, \ - region_no) + \ + TZC_REGION_OFFSET( \ + TZC_##macro_name##_REGION_SIZE, \ + (u_register_t)region_no) + \ TZC_##macro_name##_REGION_TOP_LOW_0_OFFSET, \ (uint32_t)region_top); \ mmio_write_32(base + \ TZC_REGION_OFFSET( \ TZC_##macro_name##_REGION_SIZE, \ - region_no) + \ + (u_register_t)region_no) + \ TZC_##macro_name##_REGION_TOP_HIGH_0_OFFSET, \ (uint32_t)(region_top >> 32)); \ } @@ -70,7 +70,7 @@ mmio_write_32(base + \ TZC_REGION_OFFSET( \ TZC_##macro_name##_REGION_SIZE, \ - region_no) + \ + (u_register_t)region_no) + \ TZC_##macro_name##_REGION_ATTR_0_OFFSET, \ attr); \ } @@ -84,7 +84,7 @@ mmio_write_32(base + \ TZC_REGION_OFFSET( \ TZC_##macro_name##_REGION_SIZE, \ - region_no) + \ + (u_register_t)region_no) + \ TZC_##macro_name##_REGION_ID_ACCESS_0_OFFSET, \ val); \ } diff --git a/drivers/cadence/uart/aarch64/cdns_console.S b/drivers/cadence/uart/aarch64/cdns_console.S index 8e5d6a1aab..d1995e3e68 100644 --- a/drivers/cadence/uart/aarch64/cdns_console.S +++ b/drivers/cadence/uart/aarch64/cdns_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -184,11 +184,11 @@ func console_cdns_getc endfunc console_cdns_getc /* --------------------------------------------- - * int console_cdns_core_flush(uintptr_t base_addr) + * void console_cdns_core_flush(uintptr_t base_addr) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - console base address - * Out : return -1 on error else return 0. + * Out : void * Clobber list : x0, x1 * --------------------------------------------- */ @@ -198,16 +198,15 @@ func console_cdns_core_flush ASM_ASSERT(ne) #endif /* ENABLE_ASSERTIONS */ /* Placeholder */ - mov w0, #0 ret endfunc console_cdns_core_flush /* --------------------------------------------- - * int console_cdns_flush(console_t *console) + * void console_cdns_flush(console_t *console) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - pointer to console_t structure - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : x0, x1 * --------------------------------------------- */ diff --git a/drivers/console/aarch32/skeleton_console.S b/drivers/console/aarch32/skeleton_console.S index c594f7edf3..a9e13ec44c 100644 --- a/drivers/console/aarch32/skeleton_console.S +++ b/drivers/console/aarch32/skeleton_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -149,7 +149,7 @@ endfunc console_xxx_getc * Function to force a write of all buffered * data that hasn't been output. * In : r0 - pointer to console_xxx_t struct - * Out: r0 - 0 on success, < 0 on error + * Out: void * Clobber list : r0, r1, r2, r3, r4, r5 * --------------------------------------------- */ @@ -166,11 +166,5 @@ func console_xxx_flush * all data has been flushed or there was an unrecoverable error. */ - mov r0, #0 - bx lr - - /* Jump here if an unrecoverable error has been encountered. */ -flush_error: - mov r0, #-1 bx lr endfunc console_xxx_flush diff --git a/drivers/console/aarch64/skeleton_console.S b/drivers/console/aarch64/skeleton_console.S index 9a85867757..7ea2eec9fb 100644 --- a/drivers/console/aarch64/skeleton_console.S +++ b/drivers/console/aarch64/skeleton_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -145,11 +145,11 @@ getc_error: endfunc console_xxx_getc /* --------------------------------------------- - * int console_xxx_flush(console_xxx_t *console) + * void console_xxx_flush(console_xxx_t *console) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - pointer to console_xxx_t struct - * Out: w0 - 0 on success, < 0 on error + * Out: void * Clobber list : x0, x1, x2, x3, x4, x5 * --------------------------------------------- */ @@ -166,11 +166,5 @@ func console_xxx_flush * all data has been flushed or there was an unrecoverable error. */ - mov w0, #0 - ret - - /* Jump here if an unrecoverable error has been encountered. */ -flush_error: - mov w0, #-1 ret endfunc console_xxx_flush diff --git a/drivers/console/multi_console.c b/drivers/console/multi_console.c index 0665f202f8..08b8e9fb17 100644 --- a/drivers/console/multi_console.c +++ b/drivers/console/multi_console.c @@ -119,17 +119,12 @@ int console_getc(void) return err; } -int console_flush(void) +void console_flush(void) { - int err = ERROR_NO_VALID_CONSOLE; console_t *console; for (console = console_list; console != NULL; console = console->next) if ((console->flags & console_state) && (console->flush != NULL)) { - int ret = console->flush(console); - if ((err == ERROR_NO_VALID_CONSOLE) || (ret < err)) - err = ret; + console->flush(console); } - - return err; } diff --git a/drivers/coreboot/cbmem_console/aarch64/cbmem_console.S b/drivers/coreboot/cbmem_console/aarch64/cbmem_console.S index a4a7bf8f30..db07e6c0b1 100644 --- a/drivers/coreboot/cbmem_console/aarch64/cbmem_console.S +++ b/drivers/coreboot/cbmem_console/aarch64/cbmem_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -82,20 +82,17 @@ putc_write_back: endfunc console_cbmc_putc /* ----------------------------------------------- - * int console_cbmc_flush(console_cbmc_t *console) + * void console_cbmc_flush(console_cbmc_t *console) * Flushes the CBMEM console by flushing the * console buffer from the CPU's data cache. * In: x0 - pointer to console_cbmc_t struct - * Out: x0 - 0 for success - * Clobber list: x0, x1, x2, x3, x5 + * Out: void + * Clobber list: x0, x1, x2, x3 * ----------------------------------------------- */ func console_cbmc_flush - mov x5, x30 ldr x1, [x0, #CONSOLE_T_CBMC_SIZE] ldr x0, [x0, #CONSOLE_T_BASE] add x1, x1, #8 /* add size of console header */ - bl clean_dcache_range /* (clobbers x2 and x3) */ - mov x0, #0 - ret x5 + b clean_dcache_range /* (clobbers x2 and x3) */ endfunc console_cbmc_flush diff --git a/drivers/imx/uart/imx_uart.c b/drivers/imx/uart/imx_uart.c index 2c9652d194..dfe2e92b9e 100644 --- a/drivers/imx/uart/imx_uart.c +++ b/drivers/imx/uart/imx_uart.c @@ -171,12 +171,11 @@ int console_imx_uart_core_getc(uintptr_t base_addr) * Function to force a write of all buffered * data that hasn't been output. * In : r0 - console base address - * Out : return -1 on error else return 0. + * Out : void * Clobber list : r0, r1 * --------------------------------------------- */ -int console_imx_uart_core_flush(uintptr_t base_addr) +void console_imx_uart_core_flush(uintptr_t base_addr) { - return 0; } diff --git a/drivers/marvell/uart/a3700_console.S b/drivers/marvell/uart/a3700_console.S index ecd494ca74..d184a2d244 100644 --- a/drivers/marvell/uart/a3700_console.S +++ b/drivers/marvell/uart/a3700_console.S @@ -223,25 +223,24 @@ func console_a3700_getc endfunc console_a3700_getc /* --------------------------------------------- - * int console_a3700_core_flush(uintptr_t base_addr) + * void console_a3700_core_flush(uintptr_t base_addr) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - console base address - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : x0, x1 * --------------------------------------------- */ func console_a3700_core_flush - mov w0, #0 ret endfunc console_a3700_core_flush /* --------------------------------------------- - * int console_a3700_flush(console_t *console) + * void console_a3700_flush(console_t *console) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - pointer to console_t structure - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : x0, x1 * --------------------------------------------- */ diff --git a/drivers/renesas/rcar/console/rcar_console.S b/drivers/renesas/rcar/console/rcar_console.S index 4d006b703f..29baa67a4a 100644 --- a/drivers/renesas/rcar/console/rcar_console.S +++ b/drivers/renesas/rcar/console/rcar_console.S @@ -82,15 +82,12 @@ func console_rcar_putc endfunc console_rcar_putc /* --------------------------------------------- - * int console_rcar_flush(void) + * void console_rcar_flush(void) * Function to force a write of all buffered - * data that hasn't been output. It returns 0 - * upon successful completion, otherwise it - * returns -1. + * data that hasn't been output. It returns void * Clobber list : x0, x1 * --------------------------------------------- */ func console_rcar_flush - mov w0, #0 ret endfunc console_rcar_flush diff --git a/drivers/renesas/rcar/scif/scif.S b/drivers/renesas/rcar/scif/scif.S index 064aba471c..ae26cc4023 100644 --- a/drivers/renesas/rcar/scif/scif.S +++ b/drivers/renesas/rcar/scif/scif.S @@ -305,11 +305,9 @@ func console_rcar_putc endfunc console_rcar_putc /* --------------------------------------------- - * int console_rcar_flush(void) + * void console_rcar_flush(void) * Function to force a write of all buffered - * data that hasn't been output. It returns 0 - * upon successful completion, otherwise it - * returns -1. + * data that hasn't been output. It returns void * Clobber list : x0, x1 * --------------------------------------------- */ @@ -327,6 +325,5 @@ func console_rcar_flush and w1, w1, #~(SCSCR_TE_EN + SCSCR_RE_EN) strh w1, [x0, #SCIF_SCSCR] - mov w0, #0 ret endfunc console_rcar_flush diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c index f8bc5a217a..564bd87989 100644 --- a/drivers/st/clk/stm32mp1_clk.c +++ b/drivers/st/clk/stm32mp1_clk.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved + * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ @@ -1664,28 +1664,26 @@ static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) static void stm32mp1_stgen_config(void) { - uintptr_t stgen; uint32_t cntfid0; unsigned long rate; unsigned long long counter; - stgen = fdt_get_stgen_base(); - cntfid0 = mmio_read_32(stgen + CNTFID_OFF); + cntfid0 = mmio_read_32(STGEN_BASE + CNTFID_OFF); rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K)); if (cntfid0 == rate) { return; } - mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); - counter = (unsigned long long)mmio_read_32(stgen + CNTCVL_OFF); - counter |= ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF)) << 32; + mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); + counter = (unsigned long long)mmio_read_32(STGEN_BASE + CNTCVL_OFF); + counter |= ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF)) << 32; counter = (counter * rate / cntfid0); - mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter); - mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32)); - mmio_write_32(stgen + CNTFID_OFF, rate); - mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); + mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter); + mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32)); + mmio_write_32(STGEN_BASE + CNTFID_OFF, rate); + mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); write_cntfrq((u_register_t)rate); @@ -1695,20 +1693,17 @@ static void stm32mp1_stgen_config(void) void stm32mp1_stgen_increment(unsigned long long offset_in_ms) { - uintptr_t stgen; unsigned long long cnt; - stgen = fdt_get_stgen_base(); + cnt = ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) | + mmio_read_32(STGEN_BASE + CNTCVL_OFF); - cnt = ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF) << 32) | - mmio_read_32(stgen + CNTCVL_OFF); + cnt += (offset_in_ms * mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U; - cnt += (offset_in_ms * mmio_read_32(stgen + CNTFID_OFF)) / 1000U; - - mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN); - mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)cnt); - mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(cnt >> 32)); - mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN); + mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); + mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)cnt); + mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(cnt >> 32)); + mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN); } static void stm32mp1_pkcs_config(uint32_t pkcs) diff --git a/drivers/st/clk/stm32mp_clkfunc.c b/drivers/st/clk/stm32mp_clkfunc.c index e87ab1ba74..8333f6dfbf 100644 --- a/drivers/st/clk/stm32mp_clkfunc.c +++ b/drivers/st/clk/stm32mp_clkfunc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,8 +14,6 @@ #include <drivers/st/stm32_gpio.h> #include <drivers/st/stm32mp_clkfunc.h> -#define DT_STGEN_COMPAT "st,stm32-stgen" - /* * Get the frequency of an oscillator from its name in device tree. * @param name: oscillator name @@ -169,33 +167,6 @@ int fdt_get_rcc_node(void *fdt) } /* - * Get the RCC base address from the device tree - * @return: RCC address or 0 on error - */ -uint32_t fdt_rcc_read_addr(void) -{ - int node; - void *fdt; - const fdt32_t *cuint; - - if (fdt_get_address(&fdt) == 0) { - return 0; - } - - node = fdt_get_rcc_node(fdt); - if (node < 0) { - return 0; - } - - cuint = fdt_getprop(fdt, node, "reg", NULL); - if (cuint == NULL) { - return 0; - } - - return fdt32_to_cpu(*cuint); -} - -/* * Read a series of parameters in rcc-clk section in device tree * @param prop_name: Name of the RCC property to be read * @param array: the array to store the property parameters @@ -299,33 +270,6 @@ bool fdt_get_rcc_secure_status(void) } /* - * Get the stgen base address. - * @return: address of stgen on success, and NULL value on failure. - */ -uintptr_t fdt_get_stgen_base(void) -{ - int node; - const fdt32_t *cuint; - void *fdt; - - if (fdt_get_address(&fdt) == 0) { - return 0; - } - - node = fdt_node_offset_by_compatible(fdt, -1, DT_STGEN_COMPAT); - if (node < 0) { - return 0; - } - - cuint = fdt_getprop(fdt, node, "reg", NULL); - if (cuint == NULL) { - return 0; - } - - return fdt32_to_cpu(*cuint); -} - -/* * Get the clock ID of the given node in device tree. * @param node: node offset * @return: Clock ID on success, and a negative FDT/ERRNO error code on failure. diff --git a/drivers/st/fmc/stm32_fmc2_nand.c b/drivers/st/fmc/stm32_fmc2_nand.c index dbbeee4c5b..a58a243ad6 100644 --- a/drivers/st/fmc/stm32_fmc2_nand.c +++ b/drivers/st/fmc/stm32_fmc2_nand.c @@ -26,8 +26,10 @@ #define TIMEOUT_US_1_MS 1000U /* FMC2 Compatibility */ -#define DT_FMC2_COMPAT "st,stm32mp15-fmc2" +#define DT_FMC2_EBI_COMPAT "st,stm32mp1-fmc2-ebi" +#define DT_FMC2_NFC_COMPAT "st,stm32mp1-fmc2-nfc" #define MAX_CS 2U +#define MAX_BANK 5U /* FMC2 Controller Registers */ #define FMC2_BCR1 0x00U @@ -37,6 +39,7 @@ #define FMC2_PATT 0x8CU #define FMC2_HECCR 0x94U #define FMC2_BCHISR 0x254U +#define FMC2_BCHICR 0x258U #define FMC2_BCHDSR0 0x27CU #define FMC2_BCHDSR1 0x280U #define FMC2_BCHDSR2 0x284U @@ -82,6 +85,8 @@ #define FMC2_PATT_DEFAULT 0x0A0A0A0AU /* FMC2_BCHISR register */ #define FMC2_BCHISR_DERF BIT(1) +/* FMC2_BCHICR register */ +#define FMC2_BCHICR_CLEAR_IRQ GENMASK_32(4, 0) /* FMC2_BCHDSR0 register */ #define FMC2_BCHDSR0_DUE BIT(0) #define FMC2_BCHDSR0_DEF BIT(1) @@ -500,6 +505,7 @@ static void stm32_fmc2_hwctl(struct nand_device *nand) if (nand->ecc.max_bit_corr != FMC2_ECC_HAM) { mmio_clrbits_32(fmc2_base() + FMC2_PCR, FMC2_PCR_WEN); + mmio_write_32(fmc2_base() + FMC2_BCHICR, FMC2_BCHICR_CLEAR_IRQ); } stm32_fmc2_set_ecc(true); @@ -789,23 +795,26 @@ static const struct nand_ctrl_ops ctrl_ops = { int stm32_fmc2_init(void) { - int fmc_node; - int fmc_subnode = 0; + int fmc_ebi_node; + int fmc_nfc_node; + int fmc_flash_node = 0; int nchips = 0; unsigned int i; void *fdt = NULL; const fdt32_t *cuint; struct dt_node_info info; + uintptr_t bank_address[MAX_BANK] = { 0, 0, 0, 0, 0 }; + uint8_t bank_assigned = 0; + uint8_t bank; int ret; if (fdt_get_address(&fdt) == 0) { return -FDT_ERR_NOTFOUND; } - fmc_node = dt_get_node(&info, -1, DT_FMC2_COMPAT); - if (fmc_node == -FDT_ERR_NOTFOUND) { - WARN("No FMC2 node found\n"); - return fmc_node; + fmc_ebi_node = dt_get_node(&info, -1, DT_FMC2_EBI_COMPAT); + if (fmc_ebi_node < 0) { + return fmc_ebi_node; } if (info.status == DT_DISABLED) { @@ -821,27 +830,69 @@ int stm32_fmc2_init(void) stm32_fmc2.clock_id = (unsigned long)info.clock; stm32_fmc2.reset_id = (unsigned int)info.reset; - cuint = fdt_getprop(fdt, fmc_node, "reg", NULL); + cuint = fdt_getprop(fdt, fmc_ebi_node, "ranges", NULL); if (cuint == NULL) { return -FDT_ERR_BADVALUE; } - cuint += 2; - - for (i = 0U; i < MAX_CS; i++) { - stm32_fmc2.cs[i].data_base = fdt32_to_cpu(*cuint); - stm32_fmc2.cs[i].cmd_base = fdt32_to_cpu(*(cuint + 2)); - stm32_fmc2.cs[i].addr_base = fdt32_to_cpu(*(cuint + 4)); - cuint += 6; + for (i = 0U; i < MAX_BANK; i++) { + bank = fdt32_to_cpu(*cuint); + if ((bank >= MAX_BANK) || ((bank_assigned & BIT(bank)) != 0U)) { + return -FDT_ERR_BADVALUE; + } + bank_assigned |= BIT(bank); + bank_address[bank] = fdt32_to_cpu(*(cuint + 2)); + cuint += 4; } /* Pinctrl initialization */ - if (dt_set_pinctrl_config(fmc_node) != 0) { + if (dt_set_pinctrl_config(fmc_ebi_node) != 0) { return -FDT_ERR_BADVALUE; } + /* Parse NFC controller node */ + fmc_nfc_node = fdt_node_offset_by_compatible(fdt, fmc_ebi_node, + DT_FMC2_NFC_COMPAT); + if (fmc_nfc_node < 0) { + return fmc_nfc_node; + } + + if (fdt_get_status(fmc_nfc_node) == DT_DISABLED) { + return -FDT_ERR_NOTFOUND; + } + + cuint = fdt_getprop(fdt, fmc_nfc_node, "reg", NULL); + if (cuint == NULL) { + return -FDT_ERR_BADVALUE; + } + + for (i = 0U; i < MAX_CS; i++) { + bank = fdt32_to_cpu(*cuint); + if (bank >= MAX_BANK) { + return -FDT_ERR_BADVALUE; + } + stm32_fmc2.cs[i].data_base = fdt32_to_cpu(*(cuint + 1)) + + bank_address[bank]; + + bank = fdt32_to_cpu(*(cuint + 3)); + if (bank >= MAX_BANK) { + return -FDT_ERR_BADVALUE; + } + stm32_fmc2.cs[i].cmd_base = fdt32_to_cpu(*(cuint + 4)) + + bank_address[bank]; + + bank = fdt32_to_cpu(*(cuint + 6)); + if (bank >= MAX_BANK) { + return -FDT_ERR_BADVALUE; + } + stm32_fmc2.cs[i].addr_base = fdt32_to_cpu(*(cuint + 7)) + + bank_address[bank]; + + cuint += 9; + } + /* Parse flash nodes */ - fdt_for_each_subnode(fmc_subnode, fdt, fmc_node) { + fdt_for_each_subnode(fmc_flash_node, fdt, fmc_nfc_node) { nchips++; } @@ -850,14 +901,19 @@ int stm32_fmc2_init(void) return -FDT_ERR_BADVALUE; } - fdt_for_each_subnode(fmc_subnode, fdt, fmc_node) { + fdt_for_each_subnode(fmc_flash_node, fdt, fmc_nfc_node) { /* Get chip select */ - cuint = fdt_getprop(fdt, fmc_subnode, "reg", NULL); + cuint = fdt_getprop(fdt, fmc_flash_node, "reg", NULL); if (cuint == NULL) { WARN("Chip select not well defined\n"); return -FDT_ERR_BADVALUE; } + stm32_fmc2.cs_sel = fdt32_to_cpu(*cuint); + if (stm32_fmc2.cs_sel >= MAX_CS) { + return -FDT_ERR_BADVALUE; + } + VERBOSE("NAND CS %i\n", stm32_fmc2.cs_sel); } diff --git a/drivers/st/uart/aarch32/stm32_console.S b/drivers/st/uart/aarch32/stm32_console.S index 0ed37d1bdd..686b18b969 100644 --- a/drivers/st/uart/aarch32/stm32_console.S +++ b/drivers/st/uart/aarch32/stm32_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -193,37 +193,35 @@ func console_stm32_core_getc endfunc console_stm32_core_getc /* --------------------------------------------------------------- - * int console_core_flush(uintptr_t base_addr) + * void console_core_flush(uintptr_t base_addr) * * Function to force a write of all buffered data that hasn't been * output. * * In : r0 - console base address - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : r0, r1 * --------------------------------------------------------------- */ func console_stm32_core_flush +#if ENABLE_ASSERTIONS cmp r0, #0 - beq flush_error + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ /* Check Transmit Data Register Empty */ txe_loop_3: ldr r1, [r0, #USART_ISR] tst r1, #USART_ISR_TXE beq txe_loop_3 - mov r0, #0 - bx lr -flush_error: - mov r0, #-1 bx lr endfunc console_stm32_core_flush /* ------------------------------------------------------ - * int console_stm32_flush(console_t *console) + * void console_stm32_flush(console_t *console) * Function to force a write of all buffered * data that hasn't been output. * In : r0 - pointer to console_t structure - * Out : return -1 on error else return 0. + * Out : void. * Clobber list: r0, r1 * ------------------------------------------------------ */ diff --git a/drivers/ti/uart/aarch32/16550_console.S b/drivers/ti/uart/aarch32/16550_console.S index bc0b3ab1c2..0429f87024 100644 --- a/drivers/ti/uart/aarch32/16550_console.S +++ b/drivers/ti/uart/aarch32/16550_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -232,11 +232,11 @@ func console_16550_getc endfunc console_16550_getc /* --------------------------------------------- - * int console_16550_core_flush(uintptr_t base_addr) + * void console_16550_core_flush(uintptr_t base_addr) * Function to force a write of all buffered * data that hasn't been output. * In : r0 - console base address - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : r0, r1 * --------------------------------------------- */ @@ -252,16 +252,15 @@ func console_16550_core_flush cmp r1, #(UARTLSR_TEMT | UARTLSR_THRE) bne 1b - mov r0, #0 bx lr endfunc console_16550_core_flush /* --------------------------------------------- - * int console_16550_flush(console_t *console) + * void console_16550_flush(console_t *console) * Function to force a write of all buffered * data that hasn't been output. * In : r0 - pointer to console_t structure - * Out : return -1 on error else return 0. + * Out : void * Clobber list : r0, r1 * --------------------------------------------- */ diff --git a/drivers/ti/uart/aarch64/16550_console.S b/drivers/ti/uart/aarch64/16550_console.S index 064022798c..cb2151253c 100644 --- a/drivers/ti/uart/aarch64/16550_console.S +++ b/drivers/ti/uart/aarch64/16550_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -225,11 +225,11 @@ func console_16550_getc endfunc console_16550_getc /* --------------------------------------------- - * int console_16550_core_flush(uintptr_t base_addr) + * void console_16550_core_flush(uintptr_t base_addr) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - console base address - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : x0, x1 * --------------------------------------------- */ @@ -245,16 +245,15 @@ func console_16550_core_flush cmp w1, #(UARTLSR_TEMT | UARTLSR_THRE) b.ne 1b - mov w0, #0 ret endfunc console_16550_core_flush /* --------------------------------------------- - * int console_16550_flush(console_t *console) + * void console_16550_flush(console_t *console) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - pointer to console_t structure - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : x0, x1 * --------------------------------------------- */ diff --git a/fdts/morello-fvp.dts b/fdts/morello-fvp.dts index ecbed5ebdf..2218b2aaf9 100644 --- a/fdts/morello-fvp.dts +++ b/fdts/morello-fvp.dts @@ -80,6 +80,12 @@ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; }; + virtio_rng@1c190000 { + compatible = "virtio,mmio","virtio-rng"; + reg = <0x0 0x1c190000 0x0 0x200>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + }; + ethernet@1d100000 { compatible = "smsc,lan91c111"; reg = <0x0 0x1d100000 0x0 0x10000>; diff --git a/fdts/stm32mp151.dtsi b/fdts/stm32mp151.dtsi index 2eb4a39439..8f175a6492 100644 --- a/fdts/stm32mp151.dtsi +++ b/fdts/stm32mp151.dtsi @@ -264,19 +264,34 @@ status = "disabled"; }; - fmc: nand-controller@58002000 { - compatible = "st,stm32mp15-fmc2"; - reg = <0x58002000 0x1000>, - <0x80000000 0x1000>, - <0x88010000 0x1000>, - <0x88020000 0x1000>, - <0x81000000 0x1000>, - <0x89010000 0x1000>, - <0x89020000 0x1000>; - interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + fmc: memory-controller@58002000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "st,stm32mp1-fmc2-ebi"; + reg = <0x58002000 0x1000>; clocks = <&rcc FMC_K>; resets = <&rcc FMC_R>; status = "disabled"; + + ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ + <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ + <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ + <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ + <4 0 0x80000000 0x10000000>; /* NAND */ + + nand-controller@4,0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp1-fmc2-nfc"; + reg = <4 0x00000000 0x1000>, + <4 0x08010000 0x1000>, + <4 0x08020000 0x1000>, + <4 0x01000000 0x1000>, + <4 0x09010000 0x1000>, + <4 0x09020000 0x1000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; }; qspi: spi@58003000 { diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts index 615e2cc075..a6b98b7d93 100644 --- a/fdts/stm32mp157c-ed1.dts +++ b/fdts/stm32mp157c-ed1.dts @@ -55,6 +55,10 @@ status="okay"; }; +&hash1 { + status = "okay"; +}; + &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; diff --git a/fdts/stm32mp157c-ev1.dts b/fdts/stm32mp157c-ev1.dts index 50c0b939b3..c5d12e3b23 100644 --- a/fdts/stm32mp157c-ev1.dts +++ b/fdts/stm32mp157c-ev1.dts @@ -24,11 +24,16 @@ pinctrl-names = "default"; pinctrl-0 = <&fmc_pins_a>; status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - nand: nand@0 { - reg = <0>; + nand-controller@4,0 { + status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; diff --git a/fdts/tc0.dts b/fdts/tc0.dts index 15c14cabd2..763c813cf1 100644 --- a/fdts/tc0.dts +++ b/fdts/tc0.dts @@ -106,7 +106,7 @@ memory@80000000 { device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; + reg = <0x0 0x80000000 0x0 0x7d000000>; }; psci { diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index 1032e13739..db8938ff1f 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h @@ -183,23 +183,23 @@ /* CPACR definitions */ #define CPACR_FPEN(x) ((x) << 20) -#define CPACR_FP_TRAP_PL0 U(0x1) -#define CPACR_FP_TRAP_ALL U(0x2) -#define CPACR_FP_TRAP_NONE U(0x3) +#define CPACR_FP_TRAP_PL0 UL(0x1) +#define CPACR_FP_TRAP_ALL UL(0x2) +#define CPACR_FP_TRAP_NONE UL(0x3) /* SCR definitions */ -#define SCR_TWE_BIT (U(1) << 13) -#define SCR_TWI_BIT (U(1) << 12) -#define SCR_SIF_BIT (U(1) << 9) -#define SCR_HCE_BIT (U(1) << 8) -#define SCR_SCD_BIT (U(1) << 7) -#define SCR_NET_BIT (U(1) << 6) -#define SCR_AW_BIT (U(1) << 5) -#define SCR_FW_BIT (U(1) << 4) -#define SCR_EA_BIT (U(1) << 3) -#define SCR_FIQ_BIT (U(1) << 2) -#define SCR_IRQ_BIT (U(1) << 1) -#define SCR_NS_BIT (U(1) << 0) +#define SCR_TWE_BIT (UL(1) << 13) +#define SCR_TWI_BIT (UL(1) << 12) +#define SCR_SIF_BIT (UL(1) << 9) +#define SCR_HCE_BIT (UL(1) << 8) +#define SCR_SCD_BIT (UL(1) << 7) +#define SCR_NET_BIT (UL(1) << 6) +#define SCR_AW_BIT (UL(1) << 5) +#define SCR_FW_BIT (UL(1) << 4) +#define SCR_EA_BIT (UL(1) << 3) +#define SCR_FIQ_BIT (UL(1) << 2) +#define SCR_IRQ_BIT (UL(1) << 1) +#define SCR_NS_BIT (UL(1) << 0) #define SCR_VALID_BIT_MASK U(0x33ff) #define SCR_RESET_VAL U(0x0) diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index ebe1a244a2..33e1134dd5 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -326,34 +326,34 @@ /* CPACR_El1 definitions */ #define CPACR_EL1_FPEN(x) ((x) << 20) -#define CPACR_EL1_FP_TRAP_EL0 U(0x1) -#define CPACR_EL1_FP_TRAP_ALL U(0x2) -#define CPACR_EL1_FP_TRAP_NONE U(0x3) +#define CPACR_EL1_FP_TRAP_EL0 UL(0x1) +#define CPACR_EL1_FP_TRAP_ALL UL(0x2) +#define CPACR_EL1_FP_TRAP_NONE UL(0x3) /* SCR definitions */ #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) #define SCR_TWEDEL_SHIFT U(30) #define SCR_TWEDEL_MASK ULL(0xf) #define SCR_TWEDEn_BIT (UL(1) << 29) -#define SCR_ECVEN_BIT (U(1) << 28) -#define SCR_FGTEN_BIT (U(1) << 27) -#define SCR_ATA_BIT (U(1) << 26) -#define SCR_FIEN_BIT (U(1) << 21) -#define SCR_EEL2_BIT (U(1) << 18) -#define SCR_API_BIT (U(1) << 17) -#define SCR_APK_BIT (U(1) << 16) -#define SCR_TERR_BIT (U(1) << 15) -#define SCR_TWE_BIT (U(1) << 13) -#define SCR_TWI_BIT (U(1) << 12) -#define SCR_ST_BIT (U(1) << 11) -#define SCR_RW_BIT (U(1) << 10) -#define SCR_SIF_BIT (U(1) << 9) -#define SCR_HCE_BIT (U(1) << 8) -#define SCR_SMD_BIT (U(1) << 7) -#define SCR_EA_BIT (U(1) << 3) -#define SCR_FIQ_BIT (U(1) << 2) -#define SCR_IRQ_BIT (U(1) << 1) -#define SCR_NS_BIT (U(1) << 0) +#define SCR_ECVEN_BIT (UL(1) << 28) +#define SCR_FGTEN_BIT (UL(1) << 27) +#define SCR_ATA_BIT (UL(1) << 26) +#define SCR_FIEN_BIT (UL(1) << 21) +#define SCR_EEL2_BIT (UL(1) << 18) +#define SCR_API_BIT (UL(1) << 17) +#define SCR_APK_BIT (UL(1) << 16) +#define SCR_TERR_BIT (UL(1) << 15) +#define SCR_TWE_BIT (UL(1) << 13) +#define SCR_TWI_BIT (UL(1) << 12) +#define SCR_ST_BIT (UL(1) << 11) +#define SCR_RW_BIT (UL(1) << 10) +#define SCR_SIF_BIT (UL(1) << 9) +#define SCR_HCE_BIT (UL(1) << 8) +#define SCR_SMD_BIT (UL(1) << 7) +#define SCR_EA_BIT (UL(1) << 3) +#define SCR_FIQ_BIT (UL(1) << 2) +#define SCR_IRQ_BIT (UL(1) << 1) +#define SCR_NS_BIT (UL(1) << 0) #define SCR_VALID_BIT_MASK U(0x2f8f) #define SCR_RESET_VAL SCR_RES1_BITS diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index 17a4efaf63..6f4143c5f5 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S @@ -305,7 +305,7 @@ */ pie_fixup: ldr x0, =pie_fixup - and x0, x0, #~(PAGE_SIZE - 1) + and x0, x0, #~(PAGE_SIZE_MASK) mov_imm x1, \_pie_fixup_size add x1, x1, x0 bl fixup_gdt_reloc diff --git a/include/common/debug.h b/include/common/debug.h index 9aef15b514..ed0e8bf97c 100644 --- a/include/common/debug.h +++ b/include/common/debug.h @@ -101,7 +101,7 @@ void __dead2 do_panic(void); #define panic() \ do { \ backtrace(__func__); \ - (void)console_flush(); \ + console_flush(); \ do_panic(); \ } while (false) diff --git a/include/drivers/console.h b/include/drivers/console.h index 761816ac74..99bf960418 100644 --- a/include/drivers/console.h +++ b/include/drivers/console.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -43,7 +43,7 @@ typedef struct console { u_register_t flags; int (*const putc)(int character, struct console *console); int (*const getc)(struct console *console); - int (*const flush)(struct console *console); + void (*const flush)(struct console *console); uintptr_t base; /* Additional private driver data may follow here. */ } console_t; @@ -76,7 +76,7 @@ int console_putc(int c); /* Read a character (blocking) from any console registered for current state. */ int console_getc(void); /* Flush all consoles registered for the current state. */ -int console_flush(void); +void console_flush(void); #endif /* __ASSEMBLER__ */ diff --git a/include/drivers/marvell/cache_llc.h b/include/drivers/marvell/cache_llc.h index d6dd65382f..72111b374a 100644 --- a/include/drivers/marvell/cache_llc.h +++ b/include/drivers/marvell/cache_llc.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018 Marvell International Ltd. + * Copyright (C) 2018-2020 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -57,6 +57,6 @@ int llc_sram_enable(int ap_index, int size); void llc_sram_disable(int ap_index); int llc_sram_test(int ap_index, int size, char *msg); #endif /* LLC_SRAM */ -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* CACHE_LLC_H */ diff --git a/include/drivers/st/stm32mp_clkfunc.h b/include/drivers/st/stm32mp_clkfunc.h index 0902f445d1..c7e0b6e6fb 100644 --- a/include/drivers/st/stm32mp_clkfunc.h +++ b/include/drivers/st/stm32mp_clkfunc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,14 +20,12 @@ uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id, uint32_t dflt_value); int fdt_get_rcc_node(void *fdt); -uint32_t fdt_rcc_read_addr(void); int fdt_rcc_read_uint32_array(const char *prop_name, uint32_t count, uint32_t *array); int fdt_rcc_subnode_offset(const char *name); const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp); bool fdt_get_rcc_secure_status(void); -uintptr_t fdt_get_stgen_base(void); int fdt_get_clock_id(int node); #endif /* STM32MP_CLKFUNC_H */ diff --git a/include/export/common/ep_info_exp.h b/include/export/common/ep_info_exp.h index 4c703e6de1..9d2969f3fb 100644 --- a/include/export/common/ep_info_exp.h +++ b/include/export/common/ep_info_exp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,10 +25,10 @@ #endif /* Security state of the image. */ -#define EP_SECURITY_MASK U(0x1) -#define EP_SECURITY_SHIFT U(0) -#define EP_SECURE U(0x0) -#define EP_NON_SECURE U(0x1) +#define EP_SECURITY_MASK UL(0x1) +#define EP_SECURITY_SHIFT UL(0) +#define EP_SECURE UL(0x0) +#define EP_NON_SECURE UL(0x1) /* Endianness of the image. */ #define EP_EE_MASK U(0x2) diff --git a/include/lib/coreboot.h b/include/lib/coreboot.h index dda3173a26..0aa65791dd 100644 --- a/include/lib/coreboot.h +++ b/include/lib/coreboot.h @@ -39,7 +39,7 @@ typedef enum { CB_MEM_TABLE = 16, } coreboot_memory_t; -coreboot_memory_t coreboot_get_memory_type(uintptr_t address); +coreboot_memory_t coreboot_get_memory_type(uintptr_t start, size_t size); void coreboot_table_setup(void *base); #endif /* COREBOOT_H */ diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h index 41aced8d28..ed84c0f4a1 100644 --- a/include/lib/cpus/aarch64/cortex_a77.h +++ b/include/lib/cpus/aarch64/cortex_a77.h @@ -16,6 +16,7 @@ * CPU Extended Control register specific definitions. ******************************************************************************/ #define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) #define CORTEX_A77_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) /******************************************************************************* diff --git a/include/lib/cpus/aarch64/cortex_hercules_ae.h b/include/lib/cpus/aarch64/cortex_a78_ae.h index 73c22f7326..24ae7eeacd 100644 --- a/include/lib/cpus/aarch64/cortex_hercules_ae.h +++ b/include/lib/cpus/aarch64/cortex_a78_ae.h @@ -4,11 +4,11 @@ * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef CORTEX_HERCULES_AE_H -#define CORTEX_HERCULES_AE_H +#ifndef CORTEX_A78_AE_H +#define CORTEX_A78_AE_H #include <cortex_a78.h> -#define CORTEX_HERCULES_AE_MIDR U(0x410FD420) +#define CORTEX_A78_AE_MIDR U(0x410FD420) -#endif /* CORTEX_HERCULES_AE_H */ +#endif /* CORTEX_A78_AE_H */ diff --git a/include/lib/cpus/aarch64/neoverse_zeus.h b/include/lib/cpus/aarch64/neoverse_v1.h index f0947271d9..650eb4d418 100644 --- a/include/lib/cpus/aarch64/neoverse_zeus.h +++ b/include/lib/cpus/aarch64/neoverse_v1.h @@ -1,23 +1,23 @@ /* - * Copyright (c) 2019, ARM Limited. All rights reserved. + * Copyright (c) 2019-2020, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ -#ifndef NEOVERSE_ZEUS_H -#define NEOVERSE_ZEUS_H +#ifndef NEOVERSE_V1_H +#define NEOVERSE_V1_H -#define NEOVERSE_ZEUS_MIDR U(0x410FD400) +#define NEOVERSE_V1_MIDR U(0x410FD400) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define NEOVERSE_ZEUS_CPUECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4 /******************************************************************************* * CPU Power Control register specific definitions ******************************************************************************/ -#define NEOVERSE_ZEUS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define NEOVERSE_ZEUS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +#define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) -#endif /* NEOVERSE_ZEUS_H */ +#endif /* NEOVERSE_V1_H */ diff --git a/include/lib/cpus/aarch64/rainier.h b/include/lib/cpus/aarch64/rainier.h index 9ff1669563..978661ff69 100644 --- a/include/lib/cpus/aarch64/rainier.h +++ b/include/lib/cpus/aarch64/rainier.h @@ -10,7 +10,7 @@ #include <lib/utils_def.h> /* RAINIER MIDR for revision 0 */ -#define RAINIER_MIDR U(0x3f0f4100) +#define RAINIER_MIDR U(0x3f0f4120) /* Exception Syndrome register EC code for IC Trap */ #define RAINIER_EC_IC_TRAP U(0x1f) diff --git a/include/lib/pmf/pmf.h b/include/lib/pmf/pmf.h index 3fc8e3863d..fa990d2e54 100644 --- a/include/lib/pmf/pmf.h +++ b/include/lib/pmf/pmf.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,13 +14,13 @@ /* * Constants used for/by PMF services. */ -#define PMF_ARM_TIF_IMPL_ID U(0x41) +#define PMF_ARM_TIF_IMPL_ID UL(0x41) #define PMF_TID_SHIFT 0 -#define PMF_TID_MASK (U(0xFF) << PMF_TID_SHIFT) +#define PMF_TID_MASK (UL(0xFF) << PMF_TID_SHIFT) #define PMF_SVC_ID_SHIFT 10 -#define PMF_SVC_ID_MASK (U(0x3F) << PMF_SVC_ID_SHIFT) +#define PMF_SVC_ID_MASK (UL(0x3F) << PMF_SVC_ID_SHIFT) #define PMF_IMPL_ID_SHIFT 24 -#define PMF_IMPL_ID_MASK (U(0xFF) << PMF_IMPL_ID_SHIFT) +#define PMF_IMPL_ID_MASK (UL(0xFF) << PMF_IMPL_ID_SHIFT) /* * Flags passed to PMF_REGISTER_SERVICE diff --git a/include/lib/pmf/pmf_helpers.h b/include/lib/pmf/pmf_helpers.h index cfb27f7dc0..b49c6da09e 100644 --- a/include/lib/pmf/pmf_helpers.h +++ b/include/lib/pmf/pmf_helpers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -174,24 +174,26 @@ typedef struct pmf_svc_desc { unsigned long long ts) \ { \ CASSERT(_flags != 0, select_proper_config); \ - PMF_VALIDATE_TID(_name, tid); \ + PMF_VALIDATE_TID(_name, (uint64_t)tid); \ uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \ if (((_flags) & PMF_STORE_ENABLE) != 0) \ - __pmf_store_timestamp(base_addr, tid, ts); \ + __pmf_store_timestamp(base_addr, \ + (uint64_t)tid, ts); \ if (((_flags) & PMF_DUMP_ENABLE) != 0) \ - __pmf_dump_timestamp(tid, ts); \ + __pmf_dump_timestamp((uint64_t)tid, ts); \ } \ void pmf_capture_timestamp_with_cache_maint_ ## _name( \ unsigned int tid, \ unsigned long long ts) \ { \ CASSERT(_flags != 0, select_proper_config); \ - PMF_VALIDATE_TID(_name, tid); \ + PMF_VALIDATE_TID(_name, (uint64_t)tid); \ uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \ if (((_flags) & PMF_STORE_ENABLE) != 0) \ - __pmf_store_timestamp_with_cache_maint(base_addr, tid, ts);\ + __pmf_store_timestamp_with_cache_maint( \ + base_addr, (uint64_t)tid, ts); \ if (((_flags) & PMF_DUMP_ENABLE) != 0) \ - __pmf_dump_timestamp(tid, ts); \ + __pmf_dump_timestamp((uint64_t)tid, ts); \ } /* diff --git a/include/lib/smccc.h b/include/lib/smccc.h index 366f0560b1..470317dd00 100644 --- a/include/lib/smccc.h +++ b/include/lib/smccc.h @@ -78,8 +78,8 @@ #define SMC_64 U(1) #define SMC_32 U(0) -#define SMC_TYPE_FAST ULL(1) -#define SMC_TYPE_YIELD ULL(0) +#define SMC_TYPE_FAST UL(1) +#define SMC_TYPE_YIELD UL(0) #define SMC_OK ULL(0) #define SMC_UNK -1 @@ -112,7 +112,8 @@ /* The macro below is used to identify a valid Fast SMC call */ #define is_valid_fast_smc(_fid) ((!(((_fid) >> 16) & U(0xff))) && \ - (GET_SMC_TYPE(_fid) == SMC_TYPE_FAST)) + (GET_SMC_TYPE(_fid) \ + == (uint32_t)SMC_TYPE_FAST)) /* * Macro to define UUID for services. Apart from defining and initializing a diff --git a/include/lib/xlat_tables/xlat_tables_defs.h b/include/lib/xlat_tables/xlat_tables_defs.h index 76cfc0b347..579d8d89cf 100644 --- a/include/lib/xlat_tables/xlat_tables_defs.h +++ b/include/lib/xlat_tables/xlat_tables_defs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -74,8 +74,8 @@ * 64KB. However, only 4KB are supported at the moment. */ #define PAGE_SIZE_SHIFT FOUR_KB_SHIFT -#define PAGE_SIZE (U(1) << PAGE_SIZE_SHIFT) -#define PAGE_SIZE_MASK (PAGE_SIZE - U(1)) +#define PAGE_SIZE (UL(1) << PAGE_SIZE_SHIFT) +#define PAGE_SIZE_MASK (PAGE_SIZE - UL(1)) #define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == U(0)) #if (ARM_ARCH_MAJOR == 7) && !ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index c018643066..00746c6da0 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -497,9 +497,9 @@ # elif defined(SPD_spmd) # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) -# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE -# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ - + (UL(1) << 21)) +# define BL32_BASE PLAT_ARM_SPMC_BASE +# define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ + PLAT_ARM_SPMC_SIZE) # elif ARM_BL31_IN_DRAM # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ PLAT_ARM_MAX_BL31_SIZE) diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h index 2c1a180c83..ebcc855774 100644 --- a/include/plat/common/platform.h +++ b/include/plat/common/platform.h @@ -111,7 +111,7 @@ uintptr_t plat_get_my_stack(void); void plat_report_exception(unsigned int exception_type); int plat_crash_console_init(void); int plat_crash_console_putc(int c); -int plat_crash_console_flush(void); +void plat_crash_console_flush(void); void plat_error_handler(int err) __dead2; void plat_panic_handler(void) __dead2; const char *plat_log_get_prefix(unsigned int log_level); diff --git a/lib/aarch64/misc_helpers.S b/lib/aarch64/misc_helpers.S index d298f2b667..052891683f 100644 --- a/lib/aarch64/misc_helpers.S +++ b/lib/aarch64/misc_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -496,7 +496,7 @@ func fixup_gdt_reloc /* Test if the limits are 4K aligned */ #if ENABLE_ASSERTIONS orr x0, x0, x1 - tst x0, #(PAGE_SIZE - 1) + tst x0, #(PAGE_SIZE_MASK) ASM_ASSERT(eq) #endif /* @@ -504,7 +504,7 @@ func fixup_gdt_reloc * Assume that this function is called within a page at the start of * fixup region. */ - and x2, x30, #~(PAGE_SIZE - 1) + and x2, x30, #~(PAGE_SIZE_MASK) sub x0, x2, x6 /* Diff(S) = Current Address - Compiled Address */ adrp x1, __GOT_START__ diff --git a/lib/coreboot/coreboot_table.c b/lib/coreboot/coreboot_table.c index c4cd1d752e..fb31ef1e07 100644 --- a/lib/coreboot/coreboot_table.c +++ b/lib/coreboot/coreboot_table.c @@ -89,7 +89,7 @@ static void setup_cbmem_console(uintptr_t baseaddr) CONSOLE_FLAG_CRASH); } -coreboot_memory_t coreboot_get_memory_type(uintptr_t address) +coreboot_memory_t coreboot_get_memory_type(uintptr_t start, size_t size) { int i; @@ -98,9 +98,11 @@ coreboot_memory_t coreboot_get_memory_type(uintptr_t address) if (range->type == CB_MEM_NONE) break; /* end of table reached */ - if (address >= range->start && - address - range->start < range->size) + if ((start >= range->start) && + (start - range->start < range->size) && + (size <= range->size - (start - range->start))) { return range->type; + } } return CB_MEM_NONE; diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S index ea219998f4..04a610e495 100644 --- a/lib/cpus/aarch64/cortex_a77.S +++ b/lib/cpus/aarch64/cortex_a77.S @@ -114,6 +114,35 @@ func check_errata_1800714 b cpu_rev_var_ls endfunc check_errata_1800714 + /* -------------------------------------------------- + * Errata Workaround for Cortex A77 Errata #1925769. + * This applies to revision <= r1p1 of Cortex A77. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a77_1925769_wa + /* Compare x0 against revision <= r1p1 */ + mov x17, x30 + bl check_errata_1925769 + cbz x0, 1f + + /* Set bit 8 in ECTLR_EL1 */ + mrs x1, CORTEX_A77_CPUECTLR_EL1 + orr x1, x1, #CORTEX_A77_CPUECTLR_EL1_BIT_8 + msr CORTEX_A77_CPUECTLR_EL1, x1 + isb +1: + ret x17 +endfunc errata_a77_1925769_wa + +func check_errata_1925769 + /* Applies to everything <= r1p1 */ + mov x1, #0x11 + b cpu_rev_var_ls +endfunc check_errata_1925769 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A77. * Shall clobber: x0-x19 @@ -134,6 +163,11 @@ func cortex_a77_reset_func bl errata_a77_1800714_wa #endif +#if ERRATA_A77_1925769 + mov x0, x18 + bl errata_a77_1925769_wa +#endif + ret x19 endfunc cortex_a77_reset_func @@ -169,6 +203,7 @@ func cortex_a77_errata_report */ report_errata ERRATA_A77_1508412, cortex_a77, 1508412 report_errata ERRATA_A77_1800714, cortex_a77, 1800714 + report_errata ERRATA_A77_1925769, cortex_a77, 1925769 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/aarch64/cortex_hercules_ae.S b/lib/cpus/aarch64/cortex_a78_ae.S index 4452c419a7..9aff9ac85c 100644 --- a/lib/cpus/aarch64/cortex_hercules_ae.S +++ b/lib/cpus/aarch64/cortex_a78_ae.S @@ -7,21 +7,21 @@ #include <arch.h> #include <asm_macros.S> #include <common/bl_common.h> -#include <cortex_hercules_ae.h> +#include <cortex_a78_ae.h> #include <cpu_macros.S> #include <plat_macros.S> /* Hardware handled coherency */ #if HW_ASSISTED_COHERENCY == 0 -#error "cortex_hercules_ae must be compiled with HW_ASSISTED_COHERENCY enabled" +#error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled" #endif /* ------------------------------------------------- - * The CPU Ops reset function for Cortex-Hercules-AE + * The CPU Ops reset function for Cortex-A78-AE * ------------------------------------------------- */ #if ENABLE_AMU -func cortex_hercules_ae_reset_func +func cortex_a78_ae_reset_func /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, actlr_el3 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT @@ -42,14 +42,14 @@ func cortex_hercules_ae_reset_func isb ret -endfunc cortex_hercules_ae_reset_func +endfunc cortex_a78_ae_reset_func #endif /* ------------------------------------------------------- * HW will do the cache maintenance while powering down * ------------------------------------------------------- */ -func cortex_hercules_ae_core_pwr_dwn +func cortex_a78_ae_core_pwr_dwn /* ------------------------------------------------------- * Enable CPU power down bit in power control register * ------------------------------------------------------- @@ -59,19 +59,19 @@ func cortex_hercules_ae_core_pwr_dwn msr CORTEX_A78_CPUPWRCTLR_EL1, x0 isb ret -endfunc cortex_hercules_ae_core_pwr_dwn +endfunc cortex_a78_ae_core_pwr_dwn /* - * Errata printing function for cortex_hercules_ae. Must follow AAPCS. + * Errata printing function for cortex_a78_ae. Must follow AAPCS. */ #if REPORT_ERRATA -func cortex_hercules_ae_errata_report +func cortex_a78_ae_errata_report ret -endfunc cortex_hercules_ae_errata_report +endfunc cortex_a78_ae_errata_report #endif /* ------------------------------------------------------- - * This function provides cortex_hercules_ae specific + * This function provides cortex_a78_ae specific * register information for crash reporting. * It needs to return with x6 pointing to * a list of register names in ascii and @@ -79,22 +79,22 @@ endfunc cortex_hercules_ae_errata_report * reported. * ------------------------------------------------------- */ -.section .rodata.cortex_hercules_ae_regs, "aS" -cortex_hercules_ae_regs: /* The ascii list of register names to be reported */ +.section .rodata.cortex_a78_ae_regs, "aS" +cortex_a78_ae_regs: /* The ascii list of register names to be reported */ .asciz "cpuectlr_el1", "" -func cortex_hercules_ae_cpu_reg_dump - adr x6, cortex_hercules_ae_regs +func cortex_a78_ae_cpu_reg_dump + adr x6, cortex_a78_ae_regs mrs x8, CORTEX_A78_CPUECTLR_EL1 ret -endfunc cortex_hercules_ae_cpu_reg_dump +endfunc cortex_a78_ae_cpu_reg_dump #if ENABLE_AMU -#define HERCULES_AE_RESET_FUNC cortex_hercules_ae_reset_func +#define A78_AE_RESET_FUNC cortex_a78_ae_reset_func #else -#define HERCULES_AE_RESET_FUNC CPU_NO_RESET_FUNC +#define A78_AE_RESET_FUNC CPU_NO_RESET_FUNC #endif -declare_cpu_ops cortex_hercules_ae, CORTEX_HERCULES_AE_MIDR, \ - HERCULES_AE_RESET_FUNC, \ - cortex_hercules_ae_core_pwr_dwn +declare_cpu_ops cortex_a78_ae, CORTEX_A78_AE_MIDR, \ + A78_AE_RESET_FUNC, \ + cortex_a78_ae_core_pwr_dwn diff --git a/lib/cpus/aarch64/neoverse_zeus.S b/lib/cpus/aarch64/neoverse_v1.S index 44882b4593..7336294253 100644 --- a/lib/cpus/aarch64/neoverse_zeus.S +++ b/lib/cpus/aarch64/neoverse_v1.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, ARM Limited. All rights reserved. + * Copyright (c) 2019-2020, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,46 +7,46 @@ #include <arch.h> #include <asm_macros.S> #include <common/bl_common.h> -#include <neoverse_zeus.h> +#include <neoverse_v1.h> #include <cpu_macros.S> #include <plat_macros.S> /* Hardware handled coherency */ #if HW_ASSISTED_COHERENCY == 0 -#error "Neoverse Zeus must be compiled with HW_ASSISTED_COHERENCY enabled" +#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled" #endif /* 64-bit only core */ #if CTX_INCLUDE_AARCH32_REGS == 1 -#error "Neoverse-Zeus supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- */ -func neoverse_zeus_core_pwr_dwn +func neoverse_v1_core_pwr_dwn /* --------------------------------------------- * Enable CPU power down bit in power control register * --------------------------------------------- */ - mrs x0, NEOVERSE_ZEUS_CPUPWRCTLR_EL1 - orr x0, x0, #NEOVERSE_ZEUS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr NEOVERSE_ZEUS_CPUPWRCTLR_EL1, x0 + mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1 + orr x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0 isb ret -endfunc neoverse_zeus_core_pwr_dwn +endfunc neoverse_v1_core_pwr_dwn /* - * Errata printing function for Neoverse Zeus. Must follow AAPCS. + * Errata printing function for Neoverse V1. Must follow AAPCS. */ #if REPORT_ERRATA -func neoverse_zeus_errata_report +func neoverse_v1_errata_report ret -endfunc neoverse_zeus_errata_report +endfunc neoverse_v1_errata_report #endif -func neoverse_zeus_reset_func +func neoverse_v1_reset_func mov x19, x30 /* Disable speculative loads */ @@ -54,10 +54,10 @@ func neoverse_zeus_reset_func isb ret x19 -endfunc neoverse_zeus_reset_func +endfunc neoverse_v1_reset_func /* --------------------------------------------- - * This function provides Neoverse-Zeus specific + * This function provides Neoverse-V1 specific * register information for crash reporting. * It needs to return with x6 pointing to * a list of register names in ascii and @@ -65,16 +65,16 @@ endfunc neoverse_zeus_reset_func * reported. * --------------------------------------------- */ -.section .rodata.neoverse_zeus_regs, "aS" -neoverse_zeus_regs: /* The ascii list of register names to be reported */ +.section .rodata.neoverse_v1_regs, "aS" +neoverse_v1_regs: /* The ascii list of register names to be reported */ .asciz "cpuectlr_el1", "" -func neoverse_zeus_cpu_reg_dump - adr x6, neoverse_zeus_regs - mrs x8, NEOVERSE_ZEUS_CPUECTLR_EL1 +func neoverse_v1_cpu_reg_dump + adr x6, neoverse_v1_regs + mrs x8, NEOVERSE_V1_CPUECTLR_EL1 ret -endfunc neoverse_zeus_cpu_reg_dump +endfunc neoverse_v1_cpu_reg_dump -declare_cpu_ops neoverse_zeus, NEOVERSE_ZEUS_MIDR, \ - neoverse_zeus_reset_func, \ - neoverse_zeus_core_pwr_dwn +declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \ + neoverse_v1_reset_func, \ + neoverse_v1_core_pwr_dwn diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 925ed5f08a..12105388ff 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -290,6 +290,10 @@ ERRATA_A77_1508412 ?=0 # only to revision <= r1p1 of the Cortex A77 cpu. ERRATA_A77_1800714 ?=0 +# Flag to apply erratum 1925769 workaround during reset. This erratum applies +# only to revision <= r1p1 of the Cortex A77 cpu. +ERRATA_A77_1925769 ?=0 + # Flag to apply erratum 1688305 workaround during reset. This erratum applies # to revisions r0p0 - r1p0 of the A78 cpu. ERRATA_A78_1688305 ?=0 @@ -571,6 +575,10 @@ $(eval $(call add_define,ERRATA_A77_1508412)) $(eval $(call assert_boolean,ERRATA_A77_1800714)) $(eval $(call add_define,ERRATA_A77_1800714)) +# Process ERRATA_A77_1925769 flag +$(eval $(call assert_boolean,ERRATA_A77_1925769)) +$(eval $(call add_define,ERRATA_A77_1925769)) + # Process ERRATA_A78_1688305 flag $(eval $(call assert_boolean,ERRATA_A78_1688305)) $(eval $(call add_define,ERRATA_A78_1688305)) diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index 1cb527d990..773082a85e 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -65,9 +65,13 @@ func el2_sysregs_context_save mrs x9, cptr_el2 stp x17, x9, [x0, #CTX_CNTVOFF_EL2] - mrs x10, dbgvcr32_el2 mrs x11, elr_el2 +#if CTX_INCLUDE_AARCH32_REGS + mrs x10, dbgvcr32_el2 stp x10, x11, [x0, #CTX_DBGVCR32_EL2] +#else + str x11, [x0, #CTX_ELR_EL2] +#endif mrs x14, esr_el2 mrs x15, far_el2 @@ -90,8 +94,12 @@ func el2_sysregs_context_save stp x13, x14, [x0, #CTX_ICH_VMCR_EL2] mrs x15, mdcr_el2 +#if ENABLE_SPE_FOR_LOWER_ELS mrs x16, PMSCR_EL2 stp x15, x16, [x0, #CTX_MDCR_EL2] +#else + str x15, [x0, #CTX_MDCR_EL2] +#endif mrs x17, sctlr_el2 mrs x9, spsr_el2 @@ -185,8 +193,10 @@ func el2_sysregs_context_save mrs x9, contextidr_el2 stp x17, x9, [x0, #CTX_CNTHV_TVAL_EL2] +#if CTX_INCLUDE_AARCH32_REGS mrs x10, sder32_el2 str x10, [x0, #CTX_SDER32_EL2] +#endif mrs x11, ttbr1_el2 str x11, [x0, #CTX_TTBR1_EL2] @@ -194,8 +204,10 @@ func el2_sysregs_context_save mrs x12, vdisr_el2 str x12, [x0, #CTX_VDISR_EL2] +#if CTX_INCLUDE_NEVE_REGS mrs x13, vncr_el2 str x13, [x0, #CTX_VNCR_EL2] +#endif mrs x14, vsesr_el2 str x14, [x0, #CTX_VSESR_EL2] @@ -255,8 +267,12 @@ func el2_sysregs_context_restore msr cntvoff_el2, x17 msr cptr_el2, x9 +#if CTX_INCLUDE_AARCH32_REGS ldp x10, x11, [x0, #CTX_DBGVCR32_EL2] msr dbgvcr32_el2, x10 +#else + ldr x11, [x0, #CTX_ELR_EL2] +#endif msr elr_el2, x11 ldp x14, x15, [x0, #CTX_ESR_EL2] @@ -279,9 +295,13 @@ func el2_sysregs_context_restore msr ICH_VMCR_EL2, x13 msr mair_el2, x14 +#if ENABLE_SPE_FOR_LOWER_ELS ldp x15, x16, [x0, #CTX_MDCR_EL2] - msr mdcr_el2, x15 msr PMSCR_EL2, x16 +#else + ldr x15, [x0, #CTX_MDCR_EL2] +#endif + msr mdcr_el2, x15 ldp x17, x9, [x0, #CTX_SCTLR_EL2] msr sctlr_el2, x17 @@ -374,8 +394,10 @@ func el2_sysregs_context_restore msr cnthv_tval_el2, x9 msr contextidr_el2, x10 +#if CTX_INCLUDE_AARCH32_REGS ldr x11, [x0, #CTX_SDER32_EL2] msr sder32_el2, x11 +#endif ldr x12, [x0, #CTX_TTBR1_EL2] msr ttbr1_el2, x12 @@ -383,8 +405,10 @@ func el2_sysregs_context_restore ldr x13, [x0, #CTX_VDISR_EL2] msr vdisr_el2, x13 +#if CTX_INCLUDE_NEVE_REGS ldr x14, [x0, #CTX_VNCR_EL2] msr vncr_el2, x14 +#endif ldr x15, [x0, #CTX_VSESR_EL2] msr vsesr_el2, x15 diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index e5434eb138..b460731e8c 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -710,7 +710,7 @@ void cm_write_scr_el3_bit(uint32_t security_state, assert(ctx != NULL); /* Ensure that the bit position is a valid one */ - assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U); + assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U); /* Ensure that the 'value' is only a bit wide */ assert(value <= 1U); @@ -721,7 +721,7 @@ void cm_write_scr_el3_bit(uint32_t security_state, */ state = get_el3state_ctx(ctx); scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); - scr_el3 &= ~(1U << bit_pos); + scr_el3 &= ~(1UL << bit_pos); scr_el3 |= (u_register_t)value << bit_pos; write_ctx_reg(state, CTX_SCR_EL3, scr_el3); } diff --git a/lib/libc/assert.c b/lib/libc/assert.c index 49f59db168..ff987b3be3 100644 --- a/lib/libc/assert.c +++ b/lib/libc/assert.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,7 +23,7 @@ void __dead2 __assert(const char *file, unsigned int line, { printf("ASSERT: %s:%d:%s\n", file, line, assertion); backtrace("assert"); - (void)console_flush(); + console_flush(); plat_panic_handler(); } #elif PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO @@ -31,14 +31,14 @@ void __dead2 __assert(const char *file, unsigned int line) { printf("ASSERT: %s:%d\n", file, line); backtrace("assert"); - (void)console_flush(); + console_flush(); plat_panic_handler(); } #else void __dead2 __assert(void) { backtrace("assert"); - (void)console_flush(); + console_flush(); plat_panic_handler(); } #endif diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c index 6d813774d2..9f8a08abb2 100644 --- a/lib/psci/psci_common.c +++ b/lib/psci/psci_common.c @@ -663,7 +663,8 @@ static int psci_get_ns_ep_info(entry_point_info_t *ep, mode = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ? MODE_EL2 : MODE_EL1; - ep->spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + ep->spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); } else { mode = ((ns_scr_el3 & SCR_HCE_BIT) != 0U) ? @@ -675,7 +676,8 @@ static int psci_get_ns_ep_info(entry_point_info_t *ep, */ daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT; - ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, daif); + ep->spsr = SPSR_MODE32((uint64_t)mode, entrypoint & 0x1, ee, + daif); } return PSCI_E_SUCCESS; diff --git a/lib/psci/psci_system_off.c b/lib/psci/psci_system_off.c index 141d69ef2b..002392cad2 100644 --- a/lib/psci/psci_system_off.c +++ b/lib/psci/psci_system_off.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,7 +25,7 @@ void __dead2 psci_system_off(void) psci_spd_pm->svc_system_off(); } - (void) console_flush(); + console_flush(); /* Call the platform specific hook */ psci_plat_pm_ops->system_off(); @@ -44,7 +44,7 @@ void __dead2 psci_system_reset(void) psci_spd_pm->svc_system_reset(); } - (void) console_flush(); + console_flush(); /* Call the platform specific hook */ psci_plat_pm_ops->system_reset(); @@ -77,7 +77,7 @@ u_register_t psci_system_reset2(uint32_t reset_type, u_register_t cookie) if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_system_reset != NULL)) { psci_spd_pm->svc_system_reset(); } - (void) console_flush(); + console_flush(); return (u_register_t) psci_plat_pm_ops->system_reset2((int) is_vendor, reset_type, diff --git a/lib/xlat_tables_v2/xlat_tables_utils.c b/lib/xlat_tables_v2/xlat_tables_utils.c index 30babc63f1..9fae7e917c 100644 --- a/lib/xlat_tables_v2/xlat_tables_utils.c +++ b/lib/xlat_tables_v2/xlat_tables_utils.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -472,7 +472,7 @@ int xlat_change_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va, /* * Sanity checks. */ - for (size_t i = 0U; i < pages_count; ++i) { + for (unsigned int i = 0U; i < pages_count; ++i) { const uint64_t *entry; uint64_t desc, attr_index; unsigned int level; @@ -497,8 +497,8 @@ int xlat_change_mem_attributes_ctx(const xlat_ctx_t *ctx, uintptr_t base_va, (level != XLAT_TABLE_LEVEL_MAX)) { WARN("Address 0x%lx is not mapped at the right granularity.\n", base_va); - WARN("Granularity is 0x%llx, should be 0x%x.\n", - (unsigned long long)XLAT_BLOCK_SIZE(level), PAGE_SIZE); + WARN("Granularity is 0x%lx, should be 0x%lx.\n", + XLAT_BLOCK_SIZE(level), PAGE_SIZE); return -EINVAL; } diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk index 7220a5d763..578bd59876 100644 --- a/make_helpers/defaults.mk +++ b/make_helpers/defaults.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2016-2020, ARM Limited. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -62,6 +62,11 @@ CTX_INCLUDE_FPREGS := 0 # world. It is not needed to use it in the Non-secure world. CTX_INCLUDE_PAUTH_REGS := 0 +# Include Nested virtualization control (Armv8.4-NV) registers in cpu context. +# This must be set to 1 if architecture implements Nested Virtualization +# Extension and platform wants to use this feature in the Secure world +CTX_INCLUDE_NEVE_REGS := 0 + # Debug build DEBUG := 0 @@ -150,6 +155,10 @@ GICV2_G0_FOR_EL3 := 0 # by lower ELs. HANDLE_EA_EL3_FIRST := 0 +# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512. +# The default value is sha256. +HASH_ALG := sha256 + # Whether system coherency is managed in hardware, without explicit software # operations. HW_ASSISTED_COHERENCY := 0 diff --git a/plat/amlogic/common/aarch64/aml_helpers.S b/plat/amlogic/common/aarch64/aml_helpers.S index 39bff0833c..159c7d17f5 100644 --- a/plat/amlogic/common/aarch64/aml_helpers.S +++ b/plat/amlogic/common/aarch64/aml_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -78,8 +78,8 @@ func plat_crash_console_putc endfunc plat_crash_console_putc /* --------------------------------------------- - * int plat_crash_console_flush() - * Out : return -1 on error else return 0. + * void plat_crash_console_flush() + * Out : void. * Clobber list : x0, x1 * --------------------------------------------- */ diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk index ab576b6eaf..4b751fb20f 100644 --- a/plat/arm/board/arm_fpga/platform.mk +++ b/plat/arm/board/arm_fpga/platform.mk @@ -61,8 +61,8 @@ else lib/cpus/aarch64/cortex_a78.S \ lib/cpus/aarch64/neoverse_n1.S \ lib/cpus/aarch64/neoverse_e1.S \ - lib/cpus/aarch64/neoverse_zeus.S \ - lib/cpus/aarch64/cortex_hercules_ae.S \ + lib/cpus/aarch64/neoverse_v1.S \ + lib/cpus/aarch64/cortex_a78_ae.S \ lib/cpus/aarch64/cortex_a65.S \ lib/cpus/aarch64/cortex_a65ae.S \ lib/cpus/aarch64/cortex_klein.S \ diff --git a/plat/arm/board/common/board_arm_trusted_boot.c b/plat/arm/board/common/board_arm_trusted_boot.c index 8239e0d1a7..66cc3e9496 100644 --- a/plat/arm/board/common/board_arm_trusted_boot.c +++ b/plat/arm/board/common/board_arm_trusted_boot.c @@ -47,8 +47,11 @@ uintptr_t nv_cntr_base_addr[MAX_NV_CTR_IDS] = { extern unsigned char arm_rotpk_header[], arm_rotpk_hash_end[]; +#if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_REGS_ID) || ARM_CRYPTOCELL_INTEG static unsigned char rotpk_hash_der[ARM_ROTPK_HEADER_LEN + ARM_ROTPK_HASH_LEN]; +#endif +#if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_REGS_ID) /* * Return the ROTPK hash stored in dedicated registers. */ @@ -85,6 +88,7 @@ int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len, *flags = ROTPK_IS_HASH; return 0; } +#endif #if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \ (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) diff --git a/plat/arm/board/fvp/fvp_console.c b/plat/arm/board/fvp/fvp_console.c index 928b47bf16..1a6cd42026 100644 --- a/plat/arm/board/fvp/fvp_console.c +++ b/plat/arm/board/fvp/fvp_console.c @@ -49,6 +49,6 @@ void arm_console_runtime_init(void) void arm_console_runtime_end(void) { - (void)console_flush(); + console_flush(); (void)console_unregister(&fvp_runtime_console); } diff --git a/plat/arm/board/fvp/fvp_err.c b/plat/arm/board/fvp/fvp_err.c index 62ac882b00..c9b20905f6 100644 --- a/plat/arm/board/fvp/fvp_err.c +++ b/plat/arm/board/fvp/fvp_err.c @@ -37,7 +37,7 @@ __dead2 void plat_arm_error_handler(int err) break; } - (void)console_flush(); + console_flush(); /* Setup the watchdog to reset the system as soon as possible */ sp805_refresh(ARM_SP805_TWDG_BASE, 1U); diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 50f638924f..8defcf837a 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -43,6 +43,15 @@ #define PLAT_ARM_TRUSTED_DRAM_BASE UL(0x06000000) #define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */ +/* + * Max size of SPMC is 2MB for fvp. With SPMD enabled this value corresponds to + * max size of BL32 image. + */ +#if defined(SPD_spmd) +#define PLAT_ARM_SPMC_BASE PLAT_ARM_TRUSTED_DRAM_BASE +#define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ +#endif + /* virtual address used by dynamic mem_protect for chunk_base */ #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 4565d05ac8..4da0d76437 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -120,8 +120,8 @@ else lib/cpus/aarch64/cortex_a78.S \ lib/cpus/aarch64/neoverse_n1.S \ lib/cpus/aarch64/neoverse_e1.S \ - lib/cpus/aarch64/neoverse_zeus.S \ - lib/cpus/aarch64/cortex_hercules_ae.S \ + lib/cpus/aarch64/neoverse_v1.S \ + lib/cpus/aarch64/cortex_a78_ae.S \ lib/cpus/aarch64/cortex_klein.S \ lib/cpus/aarch64/cortex_matterhorn.S \ lib/cpus/aarch64/cortex_a65.S \ diff --git a/plat/arm/board/rddaniel/platform.mk b/plat/arm/board/rddaniel/platform.mk index 8909b551ca..7422d638a8 100644 --- a/plat/arm/board/rddaniel/platform.mk +++ b/plat/arm/board/rddaniel/platform.mk @@ -12,7 +12,7 @@ RDDANIEL_BASE = plat/arm/board/rddaniel PLAT_INCLUDES += -I${RDDANIEL_BASE}/include/ -SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_zeus.S +SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_v1.S BL1_SOURCES += ${SGI_CPU_SOURCES} \ ${RDDANIEL_BASE}/rddaniel_err.c diff --git a/plat/arm/board/rddanielxlr/platform.mk b/plat/arm/board/rddanielxlr/platform.mk index 61af81aab8..8cbad525c9 100644 --- a/plat/arm/board/rddanielxlr/platform.mk +++ b/plat/arm/board/rddanielxlr/platform.mk @@ -13,7 +13,7 @@ RDDANIELXLR_BASE = plat/arm/board/rddanielxlr PLAT_INCLUDES += -I${RDDANIELXLR_BASE}/include/ -SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_zeus.S +SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_v1.S BL1_SOURCES += ${SGI_CPU_SOURCES} \ ${RDDANIELXLR_BASE}/rddanielxlr_err.c diff --git a/plat/arm/board/tc0/fdts/tc0_fw_config.dts b/plat/arm/board/tc0/fdts/tc0_fw_config.dts index 381ce1fcb8..4b6abd4d19 100644 --- a/plat/arm/board/tc0/fdts/tc0_fw_config.dts +++ b/plat/arm/board/tc0/fdts/tc0_fw_config.dts @@ -14,10 +14,16 @@ tb_fw-config { load-address = <0x0 0x4001300>; - max-size = <0x200>; + max-size = <0x400>; id = <TB_FW_CONFIG_ID>; }; + tos_fw-config { + load-address = <0x0 0x04001700>; + max-size = <0x1000>; + id = <TOS_FW_CONFIG_ID>; + }; + hw-config { load-address = <0x0 0x83000000>; max-size = <0x01000000>; diff --git a/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts b/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts new file mode 100644 index 0000000000..b6c543ade2 --- /dev/null +++ b/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2020, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/dts-v1/; + +/ { + compatible = "arm,ffa-core-manifest-1.0"; + #address-cells = <2>; + #size-cells = <1>; + + attribute { + spmc_id = <0x8000>; + maj_ver = <0x1>; + min_ver = <0x0>; + exec_state = <0x0>; + load_address = <0x0 0xfd000000>; + entrypoint = <0x0 0xfd000000>; + binary_size = <0x80000>; + }; + + chosen { + linux,initrd-start = <0>; + linux,initrd-end = <0>; + }; + + hypervisor { + compatible = "hafnium,hafnium"; + vm1 { + is_ffa_partition; + debug_name = "cactus-primary"; + load_address = <0xfe000000>; + }; + vm2 { + is_ffa_partition; + debug_name = "cactus-secondary"; + load_address = <0xfe100000>; + vcpu_count = <4>; + mem_size = <1048576>; + }; + vm3 { + is_ffa_partition; + debug_name = "cactus-tertiary"; + load_address = <0xfe200000>; + vcpu_count = <4>; + mem_size = <1048576>; + }; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + /* + * SPM(Hafnium) requires secondary cpu nodes are declared in + * descending order + */ + CPU3:cpu@300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + }; + + CPU2:cpu@200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + }; + + CPU1:cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + }; + }; + + /* 32MB of TC0_TZC_DRAM1_BASE */ + memory@fd000000 { + device_type = "memory"; + reg = <0x0 0xfd000000 0x2000000>; + }; +}; diff --git a/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts b/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts index 2fd25d9b42..3df94bf92b 100644 --- a/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts +++ b/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts @@ -24,4 +24,24 @@ mbedtls_heap_addr = <0x0 0x0>; mbedtls_heap_size = <0x0>; }; + + secure-partitions { + compatible = "arm,sp"; + cactus-primary { + uuid = <0xb4b5671e 0x4a904fe1 0xb81ffb13 0xdae1dacb>; + load-address = <0xfe000000>; + owner = "SiP"; + }; + + cactus-secondary { + uuid = <0xd1582309 0xf02347b9 0x827c4464 0xf5578fc8>; + load-address = <0xfe100000>; + owner = "Plat"; + }; + + cactus-tertiary { + uuid = <0x79b55c73 0x1d8c44b9 0x859361e1 0x770ad8d2>; + load-address = <0xfe200000>; + }; + }; }; diff --git a/plat/arm/board/tc0/include/platform_def.h b/plat/arm/board/tc0/include/platform_def.h index 075c4037b9..72a035f0ab 100644 --- a/plat/arm/board/tc0/include/platform_def.h +++ b/plat/arm/board/tc0/include/platform_def.h @@ -22,6 +22,49 @@ #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ /* + * The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC, + * its base is ARM_AP_TZC_DRAM1_BASE. + * + * Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for: + * - BL32_BASE when SPD_spmd is enabled + * - Region to load Trusted OS + */ +#define TC0_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \ + TC0_TZC_DRAM1_SIZE) +#define TC0_TZC_DRAM1_SIZE UL(0x02000000) /* 32 MB */ +#define TC0_TZC_DRAM1_END (TC0_TZC_DRAM1_BASE + \ + TC0_TZC_DRAM1_SIZE - 1) + +#define TC0_NS_DRAM1_BASE ARM_DRAM1_BASE +#define TC0_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ + ARM_TZC_DRAM1_SIZE - \ + TC0_TZC_DRAM1_SIZE) +#define TC0_NS_DRAM1_END (TC0_NS_DRAM1_BASE + \ + TC0_NS_DRAM1_SIZE - 1) + +/* + * Mappings for TC0 DRAM1 (non-secure) and TC0 TZC DRAM1 (secure) + */ +#define TC0_MAP_NS_DRAM1 MAP_REGION_FLAT( \ + TC0_NS_DRAM1_BASE, \ + TC0_NS_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + + +#define TC0_MAP_TZC_DRAM1 MAP_REGION_FLAT( \ + TC0_TZC_DRAM1_BASE, \ + TC0_TZC_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) +/* + * Max size of SPMC is 2MB for tc0. With SPMD enabled this value corresponds to + * max size of BL32 image. + */ +#if defined(SPD_spmd) +#define PLAT_ARM_SPMC_BASE TC0_TZC_DRAM1_BASE +#define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ +#endif + +/* * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the * plat_arm_mmap array defined for each BL stage. */ @@ -71,7 +114,7 @@ #if TRUSTED_BOARD_BOOT # define PLAT_ARM_MAX_BL2_SIZE 0x1E000 #else -# define PLAT_ARM_MAX_BL2_SIZE 0x11000 +# define PLAT_ARM_MAX_BL2_SIZE 0x14000 #endif /* @@ -206,4 +249,18 @@ #define PLAT_ARM_TZC_NS_DEV_ACCESS \ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT)) +/* + * The first region below, TC0_TZC_DRAM1_BASE (0xfd000000) to + * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 48 MB of DRAM as + * secure. The second region gives non secure access to rest of DRAM. + */ +#define TC0_TZC_REGIONS_DEF \ + {TC0_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \ + TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ + {TC0_NS_DRAM1_BASE, TC0_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ + PLAT_ARM_TZC_NS_DEV_ACCESS} + +/* virtual address used by dynamic mem_protect for chunk_base */ +#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) + #endif /* PLATFORM_DEF_H */ diff --git a/plat/arm/board/tc0/platform.mk b/plat/arm/board/tc0/platform.mk index 05d691ee23..5d2cc38c46 100644 --- a/plat/arm/board/tc0/platform.mk +++ b/plat/arm/board/tc0/platform.mk @@ -85,6 +85,14 @@ $(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG})) # Add the TB_FW_CONFIG to FIP and specify the same to certtool $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG})) +ifeq (${SPD},spmd) +FDT_SOURCES += ${TC0_BASE}/fdts/${PLAT}_spmc_manifest.dts +TC0_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_spmc_manifest.dtb + +# Add the TOS_FW_CONFIG to FIP and specify the same to certtool +$(eval $(call TOOL_ADD_PAYLOAD,${TC0_TOS_FW_CONFIG},--tos-fw-config,${TC0_TOS_FW_CONFIG})) +endif + #Device tree TC0_HW_CONFIG_DTS := fdts/tc0.dts TC0_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb @@ -98,6 +106,8 @@ override CTX_INCLUDE_AARCH32_REGS := 0 override CTX_INCLUDE_PAUTH_REGS := 1 +override ENABLE_SPE_FOR_LOWER_ELS := 0 + include plat/arm/common/arm_common.mk include plat/arm/css/common/css_common.mk include plat/arm/soc/common/soc_css.mk diff --git a/plat/arm/board/tc0/tc0_plat.c b/plat/arm/board/tc0/tc0_plat.c index 05461928d2..e12ad56d81 100644 --- a/plat/arm/board/tc0/tc0_plat.c +++ b/plat/arm/board/tc0/tc0_plat.c @@ -38,7 +38,10 @@ const mmap_region_t plat_arm_mmap[] = { ARM_MAP_SHARED_RAM, TC0_FLASH0_RO, TC0_MAP_DEVICE, - ARM_MAP_NS_DRAM1, + TC0_MAP_NS_DRAM1, +#if defined(SPD_spmd) + TC0_MAP_TZC_DRAM1, +#endif #if ARM_BL31_IN_DRAM ARM_MAP_BL31_SEC_DRAM, #endif diff --git a/plat/arm/board/tc0/tc0_security.c b/plat/arm/board/tc0/tc0_security.c index 5f1cb1159b..f543762036 100644 --- a/plat/arm/board/tc0/tc0_security.c +++ b/plat/arm/board/tc0/tc0_security.c @@ -8,7 +8,7 @@ #include <platform_def.h> static const arm_tzc_regions_info_t tzc_regions[] = { - ARM_TZC_REGIONS_DEF, + TC0_TZC_REGIONS_DEF, {} }; diff --git a/plat/arm/common/aarch32/arm_helpers.S b/plat/arm/common/aarch32/arm_helpers.S index badddd3a99..1da2d4cadd 100644 --- a/plat/arm/common/aarch32/arm_helpers.S +++ b/plat/arm/common/aarch32/arm_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -64,10 +64,10 @@ func plat_crash_console_putc endfunc plat_crash_console_putc /* --------------------------------------------- - * int plat_crash_console_flush() + * void plat_crash_console_flush() * Function to force a write of all buffered * data that hasn't been output. - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : r0 * --------------------------------------------- */ diff --git a/plat/arm/common/aarch64/arm_helpers.S b/plat/arm/common/aarch64/arm_helpers.S index 06720589ae..b470781739 100644 --- a/plat/arm/common/aarch64/arm_helpers.S +++ b/plat/arm/common/aarch64/arm_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -66,10 +66,10 @@ func plat_crash_console_putc endfunc plat_crash_console_putc /* --------------------------------------------- - * int plat_crash_console_flush() + * void plat_crash_console_flush() * Function to force a write of all buffered * data that hasn't been output. - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : r0 * --------------------------------------------- */ diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c index 296aaf8bfd..7d9fd6c729 100644 --- a/plat/arm/common/arm_common.c +++ b/plat/arm/common/arm_common.c @@ -97,7 +97,7 @@ uint32_t arm_get_spsr_for_bl33_entry(void) * the FIP ToC and allowing the platform to have a say as * well. */ - spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); return spsr; } #else diff --git a/plat/arm/common/arm_console.c b/plat/arm/common/arm_console.c index c2281c42da..af5f11e460 100644 --- a/plat/arm/common/arm_console.c +++ b/plat/arm/common/arm_console.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -43,7 +43,7 @@ void __init arm_console_boot_init(void) void arm_console_boot_end(void) { - (void)console_flush(); + console_flush(); (void)console_unregister(&arm_boot_console); } @@ -62,5 +62,5 @@ void arm_console_runtime_init(void) void arm_console_runtime_end(void) { - (void)console_flush(); + console_flush(); } diff --git a/plat/brcm/board/common/bcm_console.c b/plat/brcm/board/common/bcm_console.c index d484a6f632..5f2009403a 100644 --- a/plat/brcm/board/common/bcm_console.c +++ b/plat/brcm/board/common/bcm_console.c @@ -39,7 +39,7 @@ void bcm_console_boot_init(void) void bcm_console_boot_end(void) { - (void)console_flush(); + console_flush(); (void)console_unregister(&bcm_boot_console); } @@ -59,7 +59,7 @@ void bcm_console_runtime_init(void) void bcm_console_runtime_end(void) { - (void)console_flush(); + console_flush(); (void)console_unregister(&bcm_runtime_console); } diff --git a/plat/brcm/board/stingray/aarch64/plat_helpers.S b/plat/brcm/board/stingray/aarch64/plat_helpers.S index 609553248e..9a2039dafd 100644 --- a/plat/brcm/board/stingray/aarch64/plat_helpers.S +++ b/plat/brcm/board/stingray/aarch64/plat_helpers.S @@ -182,7 +182,7 @@ func plat_crash_console_putc endfunc plat_crash_console_putc /* --------------------------------------------- - * int plat_crash_console_flush(void) + * void plat_crash_console_flush(void) * Function to flush crash console * Clobber list : x0, x1 * --------------------------------------------- diff --git a/plat/brcm/board/stingray/src/brcm_pm_ops.c b/plat/brcm/board/stingray/src/brcm_pm_ops.c index 090fbca538..03a604c152 100644 --- a/plat/brcm/board/stingray/src/brcm_pm_ops.c +++ b/plat/brcm/board/stingray/src/brcm_pm_ops.c @@ -323,7 +323,7 @@ static int brcm_validate_ns_entrypoint(uintptr_t entrypoint) if ((entrypoint >= BRCM_NS_DRAM1_BASE) && (entrypoint < (BRCM_NS_DRAM1_BASE + BRCM_NS_DRAM1_SIZE))) return PSCI_E_SUCCESS; -#ifndef AARCH32 +#ifdef __aarch64__ if ((entrypoint >= BRCM_DRAM2_BASE) && (entrypoint < (BRCM_DRAM2_BASE + BRCM_DRAM2_SIZE))) return PSCI_E_SUCCESS; diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c index b8a4d012e8..ba4c366a90 100644 --- a/plat/common/aarch64/plat_common.c +++ b/plat/common/aarch64/plat_common.c @@ -96,7 +96,7 @@ void plat_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie, #if HANDLE_EA_EL3_FIRST /* Skip backtrace for lower EL */ if (level != MODE_EL3) { - (void)console_flush(); + console_flush(); do_panic(); } #endif diff --git a/plat/hisilicon/hikey/aarch64/hikey_helpers.S b/plat/hisilicon/hikey/aarch64/hikey_helpers.S index 1752d3bb94..82a404ad36 100644 --- a/plat/hisilicon/hikey/aarch64/hikey_helpers.S +++ b/plat/hisilicon/hikey/aarch64/hikey_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -62,10 +62,10 @@ func plat_crash_console_putc endfunc plat_crash_console_putc /* --------------------------------------------- - * int plat_crash_console_flush() + * void plat_crash_console_flush() * Function to force a write of all buffered * data that hasn't been output. - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : x0, x1 * --------------------------------------------- */ diff --git a/plat/hisilicon/hikey960/aarch64/hikey960_helpers.S b/plat/hisilicon/hikey960/aarch64/hikey960_helpers.S index 606f2d0f90..5381369bc0 100644 --- a/plat/hisilicon/hikey960/aarch64/hikey960_helpers.S +++ b/plat/hisilicon/hikey960/aarch64/hikey960_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -66,10 +66,10 @@ func plat_crash_console_putc endfunc plat_crash_console_putc /* --------------------------------------------- - * int plat_crash_console_flush() + * void plat_crash_console_flush() * Function to force a write of all buffered * data that hasn't been output. - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : x0, x1 * --------------------------------------------- */ diff --git a/plat/hisilicon/poplar/aarch64/poplar_helpers.S b/plat/hisilicon/poplar/aarch64/poplar_helpers.S index 928dbefcc8..063ee64947 100644 --- a/plat/hisilicon/poplar/aarch64/poplar_helpers.S +++ b/plat/hisilicon/poplar/aarch64/poplar_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -65,10 +65,10 @@ func plat_crash_console_putc endfunc plat_crash_console_putc /* --------------------------------------------- - * int plat_crash_console_flush() + * void plat_crash_console_flush() * Function to force a write of all buffered * data that hasn't been output. - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : r0 * --------------------------------------------- */ diff --git a/plat/imx/common/imx_uart_console.S b/plat/imx/common/imx_uart_console.S index 0cb4fb8703..ceeb3a76c8 100644 --- a/plat/imx/common/imx_uart_console.S +++ b/plat/imx/common/imx_uart_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -84,6 +84,5 @@ getc_error: endfunc console_imx_uart_getc func console_imx_uart_flush - mov x0, #0 ret endfunc console_imx_uart_flush diff --git a/plat/imx/common/lpuart_console.S b/plat/imx/common/lpuart_console.S index 98b3588076..ff01e3551c 100644 --- a/plat/imx/common/lpuart_console.S +++ b/plat/imx/common/lpuart_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -72,6 +72,5 @@ getc_error: endfunc console_lpuart_getc func console_lpuart_flush - mov x0, #0 ret endfunc console_lpuart_flush diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index 8f857d1e68..814d9c6635 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -10,16 +10,20 @@ PLAT_INCLUDES := \ -Iplat/intel/soc/common/drivers/ \ -Iplat/intel/soc/common/include/ +# Include GICv2 driver files +include drivers/arm/gic/v2/gicv2.mk +AGX_GICv2_SOURCES := \ + ${GICV2_SOURCES} \ + plat/common/plat_gicv2.c + + PLAT_BL_COMMON_SOURCES := \ - drivers/arm/gic/common/gic_common.c \ - drivers/arm/gic/v2/gicv2_main.c \ - drivers/arm/gic/v2/gicv2_helpers.c \ + ${AGX_GICv2_SOURCES} \ drivers/delay_timer/delay_timer.c \ drivers/delay_timer/generic_delay_timer.c \ drivers/ti/uart/aarch64/16550_console.S \ lib/xlat_tables/aarch64/xlat_tables.c \ lib/xlat_tables/xlat_tables_common.c \ - plat/common/plat_gicv2.c \ plat/intel/soc/common/aarch64/platform_common.c \ plat/intel/soc/common/aarch64/plat_helpers.S diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index 112317b7bf..3bd6af9ce4 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -10,16 +10,20 @@ PLAT_INCLUDES := \ -Iplat/intel/soc/common/drivers/ \ -Iplat/intel/soc/common/include/ +# Include GICv2 driver files +include drivers/arm/gic/v2/gicv2.mk +AGX_GICv2_SOURCES := \ + ${GICV2_SOURCES} \ + plat/common/plat_gicv2.c + + PLAT_BL_COMMON_SOURCES := \ - drivers/arm/gic/common/gic_common.c \ - drivers/arm/gic/v2/gicv2_main.c \ - drivers/arm/gic/v2/gicv2_helpers.c \ + ${AGX_GICv2_SOURCES} \ drivers/delay_timer/delay_timer.c \ drivers/delay_timer/generic_delay_timer.c \ drivers/ti/uart/aarch64/16550_console.S \ lib/xlat_tables/aarch64/xlat_tables.c \ lib/xlat_tables/xlat_tables_common.c \ - plat/common/plat_gicv2.c \ plat/intel/soc/common/aarch64/platform_common.c \ plat/intel/soc/common/aarch64/plat_helpers.S diff --git a/plat/layerscape/common/aarch64/ls_console.S b/plat/layerscape/common/aarch64/ls_console.S index c1bd3f7316..fb8267bc07 100644 --- a/plat/layerscape/common/aarch64/ls_console.S +++ b/plat/layerscape/common/aarch64/ls_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -214,11 +214,11 @@ func console_ls_16550_getc endfunc console_ls_16550_getc /* --------------------------------------------- - * int console_ls_16550_core_flush(uintptr_t base_addr) + * void console_ls_16550_core_flush(uintptr_t base_addr) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - console base address - * Out : return -1 on error else return 0. + * Out : void * Clobber list : x0, x1 * --------------------------------------------- */ @@ -234,16 +234,15 @@ func console_ls_16550_core_flush cmp w1, #(UARTLSR_TEMT | UARTLSR_THRE) b.ne 1b - mov w0, #0 ret endfunc console_ls_16550_core_flush /* --------------------------------------------- - * int console_ls_16550_flush(console_t *console) + * void console_ls_16550_flush(console_t *console) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - pointer to console_t structure - * Out : return -1 on error else return 0. + * Out : void * Clobber list : x0, x1 * --------------------------------------------- */ diff --git a/plat/marvell/armada/common/aarch64/marvell_helpers.S b/plat/marvell/armada/common/aarch64/marvell_helpers.S index 4ddc73db50..b798f17c57 100644 --- a/plat/marvell/armada/common/aarch64/marvell_helpers.S +++ b/plat/marvell/armada/common/aarch64/marvell_helpers.S @@ -1,4 +1,5 @@ /* + * Copyright (c) 2020, ARM Limited. All rights reserved. * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause @@ -90,10 +91,10 @@ func plat_crash_console_putc endfunc plat_crash_console_putc /* --------------------------------------------- - * int plat_crash_console_flush() + * void plat_crash_console_flush() * Function to force a write of all buffered * data that hasn't been output. - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : r0 * --------------------------------------------- */ diff --git a/plat/marvell/armada/common/marvell_console.c b/plat/marvell/armada/common/marvell_console.c index 17166618af..c84b004be5 100644 --- a/plat/marvell/armada/common/marvell_console.c +++ b/plat/marvell/armada/common/marvell_console.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -49,7 +49,7 @@ void marvell_console_boot_init(void) void marvell_console_boot_end(void) { - (void)console_flush(); + console_flush(); (void)console_unregister(&marvell_boot_console); } @@ -70,7 +70,7 @@ void marvell_console_runtime_init(void) void marvell_console_runtime_end(void) { - (void)console_flush(); + console_flush(); (void)console_unregister(&marvell_runtime_console); } diff --git a/plat/mediatek/common/drivers/uart/8250_console.S b/plat/mediatek/common/drivers/uart/8250_console.S index 94a6c02ab6..7a946f9a3b 100644 --- a/plat/mediatek/common/drivers/uart/8250_console.S +++ b/plat/mediatek/common/drivers/uart/8250_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -149,16 +149,15 @@ getc_error: endfunc console_core_getc /* --------------------------------------------- - * int console_core_flush(uintptr_t base_addr) + * void console_core_flush(uintptr_t base_addr) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - console base address - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : x0, x1 * --------------------------------------------- */ func console_core_flush /* Placeholder */ - mov w0, #0 ret endfunc console_core_flush diff --git a/plat/mediatek/mt6795/aarch64/plat_helpers.S b/plat/mediatek/mt6795/aarch64/plat_helpers.S index 94f9eaef9e..aaddb2bbaa 100644 --- a/plat/mediatek/mt6795/aarch64/plat_helpers.S +++ b/plat/mediatek/mt6795/aarch64/plat_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -123,10 +123,10 @@ func plat_crash_console_putc endfunc plat_crash_console_putc /* --------------------------------------------- - * int plat_crash_console_flush(int c) + * void plat_crash_console_flush(int c) * Function to force a write of all buffered * data that hasn't been output. - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : x0, x1 * --------------------------------------------- */ diff --git a/plat/mediatek/mt8192/bl31_plat_setup.c b/plat/mediatek/mt8192/bl31_plat_setup.c index 4378c5a121..f96528196b 100644 --- a/plat/mediatek/mt8192/bl31_plat_setup.c +++ b/plat/mediatek/mt8192/bl31_plat_setup.c @@ -15,6 +15,7 @@ #include <lib/coreboot.h> /* Platform Includes */ +#include <mt_gic_v3.h> #include <plat_params.h> #include <plat_private.h> @@ -79,6 +80,9 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, ******************************************************************************/ void bl31_platform_setup(void) { + /* Initialize the GIC driver, CPU and distributor interfaces */ + mt_gic_driver_init(); + mt_gic_init(); } /******************************************************************************* diff --git a/plat/mediatek/mt8192/include/mt_gic_v3.h b/plat/mediatek/mt8192/include/mt_gic_v3.h new file mode 100644 index 0000000000..34ba8a7e35 --- /dev/null +++ b/plat/mediatek/mt8192/include/mt_gic_v3.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MT_GIC_V3_H +#define MT_GIC_V3_H + +#include <drivers/arm/gicv3.h> +#include <lib/mmio.h> + +void mt_gic_driver_init(void); +void mt_gic_init(void); +void mt_gic_set_pending(uint32_t irq); +void mt_gic_distif_save(void); +void mt_gic_distif_restore(void); +void mt_gic_rdistif_init(void); +void mt_gic_rdistif_save(void); +void mt_gic_rdistif_restore(void); +void mt_gic_rdistif_restore_all(void); +void gic_sgi_save_all(void); +void gic_sgi_restore_all(void); +#endif /* MT_GIC_V3_H */ diff --git a/plat/mediatek/mt8192/include/plat_macros.S b/plat/mediatek/mt8192/include/plat_macros.S index 92cda07756..7d17e360a8 100644 --- a/plat/mediatek/mt8192/include/plat_macros.S +++ b/plat/mediatek/mt8192/include/plat_macros.S @@ -24,8 +24,8 @@ cci_iface_regs: .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" /* --------------------------------------------- - * The below macro prints out relevant GIC and - * CCI registers whenever an unhandled exception + * The below macro prints out relevant GIC + * registers whenever an unhandled exception * is taken in BL31. * Clobbers: x0 - x10, x26, x27, sp * --------------------------------------------- diff --git a/plat/mediatek/mt8192/include/platform_def.h b/plat/mediatek/mt8192/include/platform_def.h index f68015a975..5ff013ecc9 100644 --- a/plat/mediatek/mt8192/include/platform_def.h +++ b/plat/mediatek/mt8192/include/platform_def.h @@ -39,6 +39,14 @@ #define SYS_COUNTER_FREQ_IN_MHZ 13 /******************************************************************************* + * GIC-400 & interrupt handling related constants + ******************************************************************************/ + +/* Base MTK_platform compatible GIC memory map */ +#define BASE_GICD_BASE MT_GIC_BASE +#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) + +/******************************************************************************* * Platform binary types for linking ******************************************************************************/ #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" diff --git a/plat/mediatek/mt8192/plat_mt_gic.c b/plat/mediatek/mt8192/plat_mt_gic.c new file mode 100644 index 0000000000..593f5d04e1 --- /dev/null +++ b/plat/mediatek/mt8192/plat_mt_gic.c @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2020, MediaTek Inc. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <stdint.h> +#include <stdio.h> + +#include "../drivers/arm/gic/v3/gicv3_private.h" +#include <bl31/interrupt_mgmt.h> +#include <common/bl_common.h> +#include <common/debug.h> + +#include <mt_gic_v3.h> +#include <mtk_plat_common.h> +#include <plat/common/platform.h> +#include <plat_private.h> +#include <platform_def.h> + +#define SGI_MASK 0xffff + +uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; +static uint32_t rdist_has_saved[PLATFORM_CORE_COUNT]; + +/* we save and restore the GICv3 context on system suspend */ +gicv3_dist_ctx_t dist_ctx; + +static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr) +{ + return plat_core_pos_by_mpidr(mpidr); +} + +gicv3_driver_data_t mt_gicv3_data = { + .gicd_base = MT_GIC_BASE, + .gicr_base = MT_GIC_RDIST_BASE, + .rdistif_num = PLATFORM_CORE_COUNT, + .rdistif_base_addrs = rdistif_base_addrs, + .mpidr_to_core_pos = mt_mpidr_to_core_pos, +}; + +struct gic_chip_data { + /* All cores share the same configuration */ + unsigned int saved_group; + unsigned int saved_enable; + unsigned int saved_conf0; + unsigned int saved_conf1; + unsigned int saved_grpmod; + /* Per-core sgi */ + unsigned int saved_sgi[PLATFORM_CORE_COUNT]; +}; + +static struct gic_chip_data gic_data; + +void mt_gic_driver_init(void) +{ + gicv3_driver_init(&mt_gicv3_data); +} + +void mt_gic_set_pending(uint32_t irq) +{ + gicv3_set_interrupt_pending(irq, plat_my_core_pos()); +} + +void mt_gic_distif_save(void) +{ + gicv3_distif_save(&dist_ctx); +} + +void mt_gic_distif_restore(void) +{ + gicv3_distif_init_restore(&dist_ctx); +} + +void mt_gic_rdistif_init(void) +{ + unsigned int proc_num; + unsigned int index; + uintptr_t gicr_base; + + proc_num = plat_my_core_pos(); + gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; + + /* set all SGI/PPI as non-secure GROUP1 by default */ + mmio_write_32(gicr_base + GICR_IGROUPR0, ~0U); + mmio_write_32(gicr_base + GICR_IGRPMODR0, 0x0); + + /* setup the default PPI/SGI priorities */ + for (index = 0; index < TOTAL_PCPU_INTR_NUM; index += 4U) + gicr_write_ipriorityr(gicr_base, index, + GICD_IPRIORITYR_DEF_VAL); +} + +void mt_gic_rdistif_save(void) +{ + unsigned int proc_num; + uintptr_t gicr_base; + + proc_num = plat_my_core_pos(); + gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; + + gic_data.saved_group = mmio_read_32(gicr_base + GICR_IGROUPR0); + gic_data.saved_enable = mmio_read_32(gicr_base + GICR_ISENABLER0); + gic_data.saved_conf0 = mmio_read_32(gicr_base + GICR_ICFGR0); + gic_data.saved_conf1 = mmio_read_32(gicr_base + GICR_ICFGR1); + gic_data.saved_grpmod = mmio_read_32(gicr_base + GICR_IGRPMODR0); + + rdist_has_saved[proc_num] = 1; +} + +void mt_gic_rdistif_restore(void) +{ + unsigned int proc_num; + uintptr_t gicr_base; + + proc_num = plat_my_core_pos(); + if (rdist_has_saved[proc_num] == 1) { + gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; + mmio_write_32(gicr_base + GICR_IGROUPR0, gic_data.saved_group); + mmio_write_32(gicr_base + GICR_ISENABLER0, + gic_data.saved_enable); + mmio_write_32(gicr_base + GICR_ICFGR0, gic_data.saved_conf0); + mmio_write_32(gicr_base + GICR_ICFGR1, gic_data.saved_conf1); + mmio_write_32(gicr_base + GICR_IGRPMODR0, + gic_data.saved_grpmod); + } +} + +void mt_gic_rdistif_restore_all(void) +{ + unsigned int proc_num; + uintptr_t gicr_base; + + for (proc_num = 0; proc_num < PLATFORM_CORE_COUNT; proc_num++) { + gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; + mmio_write_32(gicr_base + GICR_IGROUPR0, gic_data.saved_group); + mmio_write_32(gicr_base + GICR_ISENABLER0, + gic_data.saved_enable); + mmio_write_32(gicr_base + GICR_ICFGR0, gic_data.saved_conf0); + mmio_write_32(gicr_base + GICR_ICFGR1, gic_data.saved_conf1); + mmio_write_32(gicr_base + GICR_IGRPMODR0, + gic_data.saved_grpmod); + } +} + +void gic_sgi_save_all(void) +{ + unsigned int proc_num; + uintptr_t gicr_base; + + for (proc_num = 0; proc_num < PLATFORM_CORE_COUNT; proc_num++) { + gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; + gic_data.saved_sgi[proc_num] = + mmio_read_32(gicr_base + GICR_ISPENDR0) & SGI_MASK; + } +} + +void gic_sgi_restore_all(void) +{ + unsigned int proc_num; + uintptr_t gicr_base; + + for (proc_num = 0; proc_num < PLATFORM_CORE_COUNT; proc_num++) { + gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; + mmio_write_32(gicr_base + GICR_ICPENDR0, SGI_MASK); + mmio_write_32(gicr_base + GICR_ISPENDR0, + gic_data.saved_sgi[proc_num] & SGI_MASK); + } +} + +void mt_gic_init(void) +{ + gicv3_distif_init(); + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); +} diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk index f4ee7e7f44..c972ac61d2 100644 --- a/plat/mediatek/mt8192/platform.mk +++ b/plat/mediatek/mt8192/platform.mk @@ -10,6 +10,7 @@ MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ -I${MTK_PLAT_SOC}/include/ +GICV3_SUPPORT_GIC600 := 1 include drivers/arm/gic/v3/gicv3.mk include lib/xlat_tables_v2/xlat_tables.mk @@ -30,7 +31,8 @@ BL31_SOURCES += common/desc_image_load.c \ ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ ${MTK_PLAT_SOC}/bl31_plat_setup.c \ ${MTK_PLAT_SOC}/plat_pm.c \ - ${MTK_PLAT_SOC}/plat_topology.c + ${MTK_PLAT_SOC}/plat_topology.c \ + ${MTK_PLAT_SOC}/plat_mt_gic.c # Configs for A76 and A55 diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c index 27dd3a2901..ec34a850d9 100644 --- a/plat/nvidia/tegra/common/tegra_pm.c +++ b/plat/nvidia/tegra/common/tegra_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -138,7 +138,7 @@ static __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == PSTATE_ID_SOC_POWERDN) { INFO("%s: complete. Entering System Suspend...\n", __func__); - (void)console_flush(); + console_flush(); console_switch_state(0); } diff --git a/plat/nvidia/tegra/drivers/spe/shared_console.S b/plat/nvidia/tegra/drivers/spe/shared_console.S index 9196c1cd15..d1b18dd448 100644 --- a/plat/nvidia/tegra/drivers/spe/shared_console.S +++ b/plat/nvidia/tegra/drivers/spe/shared_console.S @@ -1,10 +1,11 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <asm_macros.S> +#include <assert_macros.S> #include <console_macros.S> #define CONSOLE_NUM_BYTES_SHIFT 24 @@ -151,33 +152,32 @@ func console_spe_getc endfunc console_spe_getc /* ------------------------------------------------- - * int console_spe_core_flush(uintptr_t base_addr) + * void console_spe_core_flush(uintptr_t base_addr) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - console base address - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : x0, x1 * ------------------------------------------------- */ func console_spe_core_flush - cbz x0, flush_error +#if ENABLE_ASSERTIONS + cmp x0, #0 + ASM_ASSERT(ne) +#endif /* ENABLE_ASSERTIONS */ /* flush console */ mov w1, #(CONSOLE_RING_DOORBELL | CONSOLE_FLUSH_DATA_TO_PORT) str w1, [x0] - mov w0, #0 - ret -flush_error: - mov w0, #-1 ret endfunc console_spe_core_flush /* --------------------------------------------- - * int console_spe_flush(console_t *console) + * void console_spe_flush(console_t *console) * Function to force a write of all buffered * data that hasn't been output. * In : x0 - pointer to console_t structure - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : x0, x1 * --------------------------------------------- */ diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v2.h b/plat/nvidia/tegra/include/drivers/memctrl_v2.h index 1e153063a6..9af3027ea3 100644 --- a/plat/nvidia/tegra/include/drivers/memctrl_v2.h +++ b/plat/nvidia/tegra/include/drivers/memctrl_v2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -26,7 +26,7 @@ #define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \ MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID) -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <assert.h> @@ -53,9 +53,9 @@ typedef struct mc_regs { .val = 0xFFFFFFFFU, \ } -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ #include <lib/mmio.h> diff --git a/plat/nvidia/tegra/include/t186/tegra_mc_def.h b/plat/nvidia/tegra/include/t186/tegra_mc_def.h index 398453eb95..fa447725ba 100644 --- a/plat/nvidia/tegra/include/t186/tegra_mc_def.h +++ b/plat/nvidia/tegra/include/t186/tegra_mc_def.h @@ -282,7 +282,7 @@ #define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1U << 24) #define MC_CLIENT_HOTRESET_STATUS1 0x974U -#ifndef __ASSEMBLY__ +#ifndef __ASSEMBLER__ /******************************************************************************* * Structure to hold the transaction override settings to use to override @@ -393,6 +393,6 @@ typedef struct mc_streamid_security_cfg { MC_TXN_OVERRIDE_CONFIG_CGID_##so_dev_axi_id); \ } while (0) -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLER__ */ #endif /* TEGRA_MC_DEF_H */ diff --git a/plat/qemu/common/aarch32/plat_helpers.S b/plat/qemu/common/aarch32/plat_helpers.S index 15e860b42f..5e346d5850 100644 --- a/plat/qemu/common/aarch32/plat_helpers.S +++ b/plat/qemu/common/aarch32/plat_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -125,10 +125,10 @@ func plat_crash_console_putc endfunc plat_crash_console_putc /* --------------------------------------------- - * int plat_crash_console_flush(int c) + * void plat_crash_console_flush(int c) * Function to force a write of all buffered * data that hasn't been output. - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : x0, x1 * --------------------------------------------- */ diff --git a/plat/qemu/common/aarch64/plat_helpers.S b/plat/qemu/common/aarch64/plat_helpers.S index dbcdc2d396..b54617385b 100644 --- a/plat/qemu/common/aarch64/plat_helpers.S +++ b/plat/qemu/common/aarch64/plat_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -121,10 +121,10 @@ func plat_crash_console_putc endfunc plat_crash_console_putc /* --------------------------------------------- - * int plat_crash_console_flush(int c) + * void plat_crash_console_flush(int c) * Function to force a write of all buffered * data that hasn't been output. - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : x0, x1 * --------------------------------------------- */ diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk index 3aa7cbe5a3..9be56a392a 100644 --- a/plat/qemu/qemu_sbsa/platform.mk +++ b/plat/qemu/qemu_sbsa/platform.mk @@ -47,9 +47,7 @@ BL1_SOURCES += drivers/io/io_semihosting.c \ ${PLAT_QEMU_COMMON_PATH}/${ARCH}/plat_helpers.S \ ${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c -BL1_SOURCES += lib/cpus/aarch64/aem_generic.S \ - lib/cpus/aarch64/cortex_a53.S \ - lib/cpus/aarch64/cortex_a57.S +BL1_SOURCES += lib/cpus/aarch64/cortex_a57.S BL2_SOURCES += drivers/io/io_semihosting.c \ drivers/io/io_storage.c \ @@ -75,9 +73,7 @@ QEMU_GIC_SOURCES := ${GICV3_SOURCES} \ plat/common/plat_gicv3.c \ ${PLAT_QEMU_COMMON_PATH}/qemu_gicv3.c -BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \ - lib/cpus/aarch64/cortex_a53.S \ - lib/cpus/aarch64/cortex_a57.S \ +BL31_SOURCES += lib/cpus/aarch64/cortex_a57.S \ lib/semihosting/semihosting.c \ lib/semihosting/${ARCH}/semihosting_call.S \ plat/common/plat_psci_common.c \ diff --git a/plat/qti/common/inc/qti_board_def.h b/plat/qti/common/inc/qti_board_def.h index 4c84661b70..c95e4c0c30 100644 --- a/plat/qti/common/inc/qti_board_def.h +++ b/plat/qti/common/inc/qti_board_def.h @@ -12,6 +12,14 @@ * development platforms */ +/* + * Defines used to retrieve QTI SOC Version + */ +#define JEDEC_QTI_BKID U(0x0) +#define JEDEC_QTI_MFID U(0x70) +#define QTI_SOC_CONTINUATION_SHIFT U(24) +#define QTI_SOC_IDENTIFICATION_SHIFT U(16) + /* Size of cacheable stacks */ #define PLATFORM_STACK_SIZE 0x1000 diff --git a/plat/qti/common/src/qti_common.c b/plat/qti/common/src/qti_common.c index ff0fa3060f..9355eb774a 100644 --- a/plat/qti/common/src/qti_common.c +++ b/plat/qti/common/src/qti_common.c @@ -11,7 +11,10 @@ #include <stdint.h> #include <common/debug.h> +#include <lib/mmio.h> +#include <lib/smccc.h> #include <lib/xlat_tables/xlat_tables_v2.h> +#include <services/arm_arch_svc.h> #include <platform_def.h> #include <qti_plat.h> @@ -146,3 +149,46 @@ int qti_mmap_remove_dynamic_region(uintptr_t base_va, size_t size) qti_align_mem_region(base_va, size, &base_va, &size); return mmap_remove_dynamic_region(base_va, size); } + +/* + * This function returns soc version which mainly consist of below fields + * + * soc_version[30:24] = JEP-106 continuation code for the SiP + * soc_version[23:16] = JEP-106 identification code with parity bit for the SiP + * soc_version[0:15] = Implementation defined SoC ID + */ +int32_t plat_get_soc_version(void) +{ + uint32_t soc_version = (QTI_SOC_VERSION & QTI_SOC_VERSION_MASK); + uint32_t jep106az_code = (JEDEC_QTI_BKID << QTI_SOC_CONTINUATION_SHIFT) + | (JEDEC_QTI_MFID << QTI_SOC_IDENTIFICATION_SHIFT); + return (int32_t)(jep106az_code | (soc_version)); +} + +/* + * This function returns soc revision in below format + * + * soc_revision[0:30] = SOC revision of specific SOC + */ +int32_t plat_get_soc_revision(void) +{ + return mmio_read_32(QTI_SOC_REVISION_REG) & QTI_SOC_REVISION_MASK; +} + +/***************************************************************************** + * plat_smccc_feature_available() - This function checks whether SMCCC feature + * is availabile for the platform or not. + * @fid: SMCCC function id + * + * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and + * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. + *****************************************************************************/ +int32_t plat_smccc_feature_available(u_register_t fid) +{ + switch (fid) { + case SMCCC_ARCH_SOC_ID: + return SMC_ARCH_CALL_SUCCESS; + default: + return SMC_ARCH_CALL_NOT_SUPPORTED; + } +} diff --git a/plat/qti/common/src/qti_syscall.c b/plat/qti/common/src/qti_syscall.c index 27c48959f8..a7601b6577 100644 --- a/plat/qti/common/src/qti_syscall.c +++ b/plat/qti/common/src/qti_syscall.c @@ -27,7 +27,7 @@ */ #define QTI_SIP_SVC_CALL_COUNT_ID U(0x0200ff00) #define QTI_SIP_SVC_UID_ID U(0x0200ff01) -/* 0x8200ff02 is reserved */ +/* 0x8200ff02 is reserved*/ #define QTI_SIP_SVC_VERSION_ID U(0x0200ff03) /* @@ -97,37 +97,52 @@ bool qti_mem_assign_validate_param(memprot_info_t *mem_info, || (src_vm_list_cnt >= QTI_VM_LAST) || (dst_vm_list_cnt == 0) || (dst_vm_list_cnt >= QTI_VM_LAST) || (u_num_mappings == 0) || u_num_mappings > QTI_VM_MAX_LIST_SIZE) { + ERROR("vm count is 0 or more then QTI_VM_LAST or empty list\n"); + ERROR("source_vm_list %p dest_vm_list %p mem_info %p src_vm_list_cnt %u dst_vm_list_cnt %u u_num_mappings %u\n", + source_vm_list, dest_vm_list, mem_info, + (unsigned int)src_vm_list_cnt, + (unsigned int)dst_vm_list_cnt, + (unsigned int)u_num_mappings); return false; } for (i = 0; i < u_num_mappings; i++) { if ((mem_info[i].mem_addr & (SIZE4K - 1)) + || (mem_info[i].mem_size == 0) || (mem_info[i].mem_size & (SIZE4K - 1))) { + ERROR("mem_info passed buffer 0x%x or size 0x%x is not 4k aligned\n", + (unsigned int)mem_info[i].mem_addr, + (unsigned int)mem_info[i].mem_size); return false; } if ((mem_info[i].mem_addr + mem_info[i].mem_size) < mem_info[i].mem_addr) { + ERROR("overflow in mem_addr 0x%x add mem_size 0x%x\n", + (unsigned int)mem_info[i].mem_addr, + (unsigned int)mem_info[i].mem_size); return false; } - if (coreboot_get_memory_type(mem_info[i].mem_addr) != - CB_MEM_RAM) { + coreboot_memory_t mem_type = coreboot_get_memory_type( + mem_info[i].mem_addr, + mem_info[i].mem_size); + if (mem_type != CB_MEM_RAM && mem_type != CB_MEM_RESERVED) { + ERROR("memory region not in CB MEM RAM or RESERVED area: region start 0x%x size 0x%x\n", + (unsigned int)mem_info[i].mem_addr, + (unsigned int)mem_info[i].mem_size); return false; } - - if (coreboot_get_memory_type - (mem_info[i].mem_addr + mem_info[i].mem_size) != - CB_MEM_RAM) { - return false; - } - } for (i = 0; i < src_vm_list_cnt; i++) { if (source_vm_list[i] >= QTI_VM_LAST) { + ERROR("source_vm_list[%d] 0x%x is more then QTI_VM_LAST\n", + i, (unsigned int)source_vm_list[i]); return false; } } for (i = 0; i < dst_vm_list_cnt; i++) { if (dest_vm_list[i].dst_vm >= QTI_VM_LAST) { + ERROR("dest_vm_list[%d] 0x%x is more then QTI_VM_LAST\n", + i, (unsigned int)dest_vm_list[i].dst_vm); return false; } } @@ -150,6 +165,7 @@ static uintptr_t qti_sip_mem_assign(void *handle, uint32_t smc_cc, } /* Validate input arg count & retrieve arg3-6 from NS Buffer. */ if ((x1 != QTI_SIP_SVC_MEM_ASSIGN_PARAM_ID) || (x5 == 0x0)) { + ERROR("invalid mem_assign param id or no mapping info\n"); goto unmap_return; } @@ -160,6 +176,8 @@ static uintptr_t qti_sip_mem_assign(void *handle, uint32_t smc_cc, SMC_32) ? (sizeof(uint32_t) * 4) : (sizeof(uint64_t) * 4); if (qti_mmap_add_dynamic_region(dyn_map_start, dyn_map_size, (MT_NS | MT_RO_DATA)) != 0) { + ERROR("map failed for params NS Buffer %x %x\n", + (unsigned int)dyn_map_start, (unsigned int)dyn_map_size); goto unmap_return; } /* Retrieve indirect args. */ @@ -174,6 +192,8 @@ static uintptr_t qti_sip_mem_assign(void *handle, uint32_t smc_cc, } /* Un-Map NS Buffer. */ if (qti_mmap_remove_dynamic_region(dyn_map_start, dyn_map_size) != 0) { + ERROR("unmap failed for params NS Buffer %x %x\n", + (unsigned int)dyn_map_start, (unsigned int)dyn_map_size); goto unmap_return; } @@ -191,6 +211,8 @@ static uintptr_t qti_sip_mem_assign(void *handle, uint32_t smc_cc, if (qti_mmap_add_dynamic_region(dyn_map_start, dyn_map_size, (MT_NS | MT_RO_DATA)) != 0) { + ERROR("map failed for params NS Buffer2 %x %x\n", + (unsigned int)dyn_map_start, (unsigned int)dyn_map_size); goto unmap_return; } memprot_info_t *mem_info_p = (memprot_info_t *) x2; @@ -205,6 +227,7 @@ static uintptr_t qti_sip_mem_assign(void *handle, uint32_t smc_cc, source_vm_list_p, src_vm_list_cnt, dest_vm_list_p, dst_vm_list_cnt) != true) { + ERROR("Param validation failed\n"); goto unmap_return; } @@ -219,8 +242,7 @@ static uintptr_t qti_sip_mem_assign(void *handle, uint32_t smc_cc, for (int i = 0; i < dst_vm_list_cnt; i++) { dest_vm_list[i].dst_vm = dest_vm_list_p[i].dst_vm; - dest_vm_list[i].dst_vm_perm = - dest_vm_list_p[i].dst_vm_perm; + dest_vm_list[i].dst_vm_perm = dest_vm_list_p[i].dst_vm_perm; dest_vm_list[i].ctx = dest_vm_list_p[i].ctx; dest_vm_list[i].ctx_size = dest_vm_list_p[i].ctx_size; } @@ -233,6 +255,8 @@ static uintptr_t qti_sip_mem_assign(void *handle, uint32_t smc_cc, /* Un-Map NS Buffers. */ if (qti_mmap_remove_dynamic_region(dyn_map_start, dyn_map_size) != 0) { + ERROR("unmap failed for params NS Buffer %x %x\n", + (unsigned int)dyn_map_start, (unsigned int)dyn_map_size); goto unmap_return; } /* Invoke API lib api. */ diff --git a/plat/qti/qtiseclib/inc/qtiseclib_cb_interface.h b/plat/qti/qtiseclib/inc/qtiseclib_cb_interface.h index 2252557a0b..deef41c5b3 100644 --- a/plat/qti/qtiseclib/inc/qtiseclib_cb_interface.h +++ b/plat/qti/qtiseclib/inc/qtiseclib_cb_interface.h @@ -44,7 +44,7 @@ void qtiseclib_cb_switch_console_to_crash_state(void); void qtiseclib_cb_udelay(uint32_t usec); -int qtiseclib_cb_console_flush(void); +void qtiseclib_cb_console_flush(void); #if QTI_SDI_BUILD int qtiseclib_cb_mmap_remove_dynamic_region(uintptr_t base_va, size_t size); diff --git a/plat/qti/qtiseclib/inc/sc7180/qtiseclib_defs_plat.h b/plat/qti/qtiseclib/inc/sc7180/qtiseclib_defs_plat.h index c695c190dd..3ecee2022c 100644 --- a/plat/qti/qtiseclib/inc/sc7180/qtiseclib_defs_plat.h +++ b/plat/qti/qtiseclib/inc/sc7180/qtiseclib_defs_plat.h @@ -13,12 +13,6 @@ #define BL31_BASE 0x80b00000 #define BL31_SIZE 0x00100000 -/*----------------------------------------------------------------------------*/ -/* AOP CMD DB address space for mapping */ -/*----------------------------------------------------------------------------*/ -#define QTI_AOP_CMD_DB_BASE 0x80820000 -#define QTI_AOP_CMD_DB_SIZE 0x00020000 - /* Chipset specific secure interrupt number/ID defs. */ #define QTISECLIB_INT_ID_SEC_WDOG_BARK (0x204) #define QTISECLIB_INT_ID_NON_SEC_WDOG_BITE (0x21) diff --git a/plat/qti/qtiseclib/src/qtiseclib_cb_interface.c b/plat/qti/qtiseclib/src/qtiseclib_cb_interface.c index 331a104b2a..bb552c66bc 100644 --- a/plat/qti/qtiseclib/src/qtiseclib_cb_interface.c +++ b/plat/qti/qtiseclib/src/qtiseclib_cb_interface.c @@ -121,7 +121,7 @@ void qtiseclib_cb_udelay(uint32_t usec) udelay(usec); } -int qtiseclib_cb_console_flush(void) +void qtiseclib_cb_console_flush(void) { return console_flush(); } diff --git a/plat/qti/sc7180/inc/platform_def.h b/plat/qti/sc7180/inc/platform_def.h index 17e1310b08..b0798a63f7 100644 --- a/plat/qti/sc7180/inc/platform_def.h +++ b/plat/qti/sc7180/inc/platform_def.h @@ -178,5 +178,17 @@ /*----------------------------------------------------------------------------*/ #define QTI_PS_HOLD_REG 0x0C264000 /*----------------------------------------------------------------------------*/ +/* AOP CMD DB address space for mapping */ +/*----------------------------------------------------------------------------*/ +#define QTI_AOP_CMD_DB_BASE 0x80820000 +#define QTI_AOP_CMD_DB_SIZE 0x00020000 +/*----------------------------------------------------------------------------*/ +/* SOC hw version register */ +/*----------------------------------------------------------------------------*/ +#define QTI_SOC_VERSION U(0x7180) +#define QTI_SOC_VERSION_MASK U(0xFFFF) +#define QTI_SOC_REVISION_REG 0x1FC8000 +#define QTI_SOC_REVISION_MASK U(0xFFFF) +/*----------------------------------------------------------------------------*/ #endif /* PLATFORM_DEF_H */ diff --git a/plat/renesas/rcar/aarch64/plat_helpers.S b/plat/renesas/rcar/aarch64/plat_helpers.S index 138d988075..ec21f2510c 100644 --- a/plat/renesas/rcar/aarch64/plat_helpers.S +++ b/plat/renesas/rcar/aarch64/plat_helpers.S @@ -295,7 +295,7 @@ func plat_crash_console_putc endfunc plat_crash_console_putc /* --------------------------------------------- - * int plat_crash_console_flush() + * void plat_crash_console_flush() * --------------------------------------------- */ func plat_crash_console_flush diff --git a/plat/rpi/common/aarch64/plat_helpers.S b/plat/rpi/common/aarch64/plat_helpers.S index e21233a1d6..f045e21139 100644 --- a/plat/rpi/common/aarch64/plat_helpers.S +++ b/plat/rpi/common/aarch64/plat_helpers.S @@ -183,10 +183,10 @@ func plat_crash_console_putc endfunc plat_crash_console_putc /* --------------------------------------------- - * int plat_crash_console_flush() + * void plat_crash_console_flush() * Function to force a write of all buffered * data that hasn't been output. - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : x0, x1 * --------------------------------------------- */ diff --git a/plat/socionext/synquacer/sq_helpers.S b/plat/socionext/synquacer/sq_helpers.S index 558aa15f68..7a2d97b33e 100644 --- a/plat/socionext/synquacer/sq_helpers.S +++ b/plat/socionext/synquacer/sq_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -98,10 +98,10 @@ func plat_crash_console_putc endfunc plat_crash_console_putc /* - * int plat_crash_console_flush(int c) + * void plat_crash_console_flush(int c) * Function to force a write of all buffered * data that hasn't been output. - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : x0, x1 */ func plat_crash_console_flush diff --git a/plat/socionext/uniphier/uniphier_console.S b/plat/socionext/uniphier/uniphier_console.S index f3dde0cc1c..48927f4145 100644 --- a/plat/socionext/uniphier/uniphier_console.S +++ b/plat/socionext/uniphier/uniphier_console.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -61,6 +61,5 @@ func uniphier_console_flush 0: ldr w1, [x0, #UNIPHIER_UART_LSR] tbz w1, #UNIPHIER_UART_LSR_TEMT_BIT, 0b - mov w0, #0 ret endfunc uniphier_console_flush diff --git a/plat/socionext/uniphier/uniphier_console_setup.c b/plat/socionext/uniphier/uniphier_console_setup.c index e2ae8bf286..9fda26e938 100644 --- a/plat/socionext/uniphier/uniphier_console_setup.c +++ b/plat/socionext/uniphier/uniphier_console_setup.c @@ -20,7 +20,7 @@ /* These callbacks are implemented in assembly to use crash_console_helpers.S */ int uniphier_console_putc(int character, struct console *console); int uniphier_console_getc(struct console *console); -int uniphier_console_flush(struct console *console); +void uniphier_console_flush(struct console *console); static console_t uniphier_console = { .flags = CONSOLE_FLAG_BOOT | diff --git a/plat/st/common/include/stm32mp_dt.h b/plat/st/common/include/stm32mp_dt.h index 44ad820dc5..e3b4e597ee 100644 --- a/plat/st/common/include/stm32mp_dt.h +++ b/plat/st/common/include/stm32mp_dt.h @@ -34,11 +34,7 @@ void dt_fill_device_info(struct dt_node_info *info, int node); int dt_get_node(struct dt_node_info *info, int offset, const char *compat); int dt_get_stdout_uart_info(struct dt_node_info *info); uint32_t dt_get_ddr_size(void); -uintptr_t dt_get_ddrctrl_base(void); -uintptr_t dt_get_ddrphyc_base(void); -uintptr_t dt_get_pwr_base(void); uint32_t dt_get_pwr_vdd_voltage(void); -uintptr_t dt_get_syscfg_base(void); const char *dt_get_board_model(void); int fdt_get_gpio_bank_pin_count(unsigned int bank); diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c index 48a747c7c2..89d8078386 100644 --- a/plat/st/common/stm32mp_common.c +++ b/plat/st/common/stm32mp_common.c @@ -39,54 +39,22 @@ uintptr_t stm32mp_get_boot_ctx_address(void) uintptr_t stm32mp_ddrctrl_base(void) { - static uintptr_t ddrctrl_base; - - if (ddrctrl_base == 0) { - ddrctrl_base = dt_get_ddrctrl_base(); - - assert(ddrctrl_base == DDRCTRL_BASE); - } - - return ddrctrl_base; + return DDRCTRL_BASE; } uintptr_t stm32mp_ddrphyc_base(void) { - static uintptr_t ddrphyc_base; - - if (ddrphyc_base == 0) { - ddrphyc_base = dt_get_ddrphyc_base(); - - assert(ddrphyc_base == DDRPHYC_BASE); - } - - return ddrphyc_base; + return DDRPHYC_BASE; } uintptr_t stm32mp_pwr_base(void) { - static uintptr_t pwr_base; - - if (pwr_base == 0) { - pwr_base = dt_get_pwr_base(); - - assert(pwr_base == PWR_BASE); - } - - return pwr_base; + return PWR_BASE; } uintptr_t stm32mp_rcc_base(void) { - static uintptr_t rcc_base; - - if (rcc_base == 0) { - rcc_base = fdt_rcc_read_addr(); - - assert(rcc_base == RCC_BASE); - } - - return rcc_base; + return RCC_BASE; } bool stm32mp_lock_available(void) diff --git a/plat/st/common/stm32mp_dt.c b/plat/st/common/stm32mp_dt.c index 4b8b2db909..391e5f0547 100644 --- a/plat/st/common/stm32mp_dt.c +++ b/plat/st/common/stm32mp_dt.c @@ -113,26 +113,6 @@ static int fdt_get_node_parent_address_cells(int node) return fdt_address_cells(fdt, parent); } - -/******************************************************************************* - * This function returns the size cells from the node parent. - * Returns: - * - #size-cells value if success. - * - invalid value if error. - * - a default value if undefined #size-cells property as per libfdt - * implementation. - ******************************************************************************/ -static int fdt_get_node_parent_size_cells(int node) -{ - int parent; - - parent = fdt_parent_offset(fdt, node); - if (parent < 0) { - return -FDT_ERR_NOTFOUND; - } - - return fdt_size_cells(fdt, parent); -} #endif /******************************************************************************* @@ -241,81 +221,6 @@ uint32_t dt_get_ddr_size(void) } /******************************************************************************* - * This function gets DDRCTRL base address information from the DT. - * Returns value on success, and 0 on failure. - ******************************************************************************/ -uintptr_t dt_get_ddrctrl_base(void) -{ - int node; - uint32_t array[4]; - - node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT); - if (node < 0) { - INFO("%s: Cannot read DDR node in DT\n", __func__); - return 0; - } - - assert((fdt_get_node_parent_address_cells(node) == 1) && - (fdt_get_node_parent_size_cells(node) == 1)); - - if (fdt_read_uint32_array(fdt, node, "reg", 4, array) < 0) { - return 0; - } - - return array[0]; -} - -/******************************************************************************* - * This function gets DDRPHYC base address information from the DT. - * Returns value on success, and 0 on failure. - ******************************************************************************/ -uintptr_t dt_get_ddrphyc_base(void) -{ - int node; - uint32_t array[4]; - - node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT); - if (node < 0) { - INFO("%s: Cannot read DDR node in DT\n", __func__); - return 0; - } - - assert((fdt_get_node_parent_address_cells(node) == 1) && - (fdt_get_node_parent_size_cells(node) == 1)); - - if (fdt_read_uint32_array(fdt, node, "reg", 4, array) < 0) { - return 0; - } - - return array[2]; -} - -/******************************************************************************* - * This function gets PWR base address information from the DT. - * Returns value on success, and 0 on failure. - ******************************************************************************/ -uintptr_t dt_get_pwr_base(void) -{ - int node; - const fdt32_t *cuint; - - node = fdt_node_offset_by_compatible(fdt, -1, DT_PWR_COMPAT); - if (node < 0) { - INFO("%s: Cannot read PWR node in DT\n", __func__); - return 0; - } - - assert(fdt_get_node_parent_address_cells(node) == 1); - - cuint = fdt_getprop(fdt, node, "reg", NULL); - if (cuint == NULL) { - return 0; - } - - return fdt32_to_cpu(*cuint); -} - -/******************************************************************************* * This function gets PWR VDD regulator voltage information from the DT. * Returns value in microvolts on success, and 0 on failure. ******************************************************************************/ @@ -355,31 +260,6 @@ uint32_t dt_get_pwr_vdd_voltage(void) } /******************************************************************************* - * This function gets SYSCFG base address information from the DT. - * Returns value on success, and 0 on failure. - ******************************************************************************/ -uintptr_t dt_get_syscfg_base(void) -{ - int node; - const fdt32_t *cuint; - - node = fdt_node_offset_by_compatible(fdt, -1, DT_SYSCFG_COMPAT); - if (node < 0) { - INFO("%s: Cannot read SYSCFG node in DT\n", __func__); - return 0; - } - - assert(fdt_get_node_parent_address_cells(node) == 1); - - cuint = fdt_getprop(fdt, node, "reg", NULL); - if (cuint == NULL) { - return 0; - } - - return fdt32_to_cpu(*cuint); -} - -/******************************************************************************* * This function retrieves board model from DT * Returns string taken from model node, NULL otherwise ******************************************************************************/ diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk index 41eacc8fde..359581925a 100644 --- a/plat/st/stm32mp1/platform.mk +++ b/plat/st/stm32mp1/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -13,12 +13,10 @@ STM32_TF_VERSION ?= 0 # Enable dynamic memory mapping PLAT_XLAT_TABLES_DYNAMIC := 1 -$(eval $(call assert_boolean,PLAT_XLAT_TABLES_DYNAMIC)) -$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC)) ifeq ($(AARCH32_SP),sp_min) # Disable Neon support: sp_min runtime may conflict with non-secure world -TF_CFLAGS += -mfloat-abi=soft +TF_CFLAGS += -mfloat-abi=soft endif # Not needed for Cortex-A7 @@ -26,13 +24,15 @@ WORKAROUND_CVE_2017_5715:= 0 # Number of TF-A copies in the device STM32_TF_A_COPIES := 2 -$(eval $(call add_define,STM32_TF_A_COPIES)) +STM32_BL33_PARTS_NUM := 1 ifeq ($(AARCH32_SP),optee) -PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + 4))) +STM32_RUNTIME_PARTS_NUM := 3 else -PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + 1))) +STM32_RUNTIME_PARTS_NUM := 0 endif -$(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES)) +PLAT_PARTITION_MAX_ENTRIES := $(shell echo $$(($(STM32_TF_A_COPIES) + \ + $(STM32_BL33_PARTS_NUM) + \ + $(STM32_RUNTIME_PARTS_NUM)))) # Boot devices STM32MP_EMMC ?= 0 @@ -46,32 +46,60 @@ ifeq ($(filter 1,${STM32MP_EMMC} ${STM32MP_SDMMC} ${STM32MP_RAW_NAND} \ $(error "No boot device driver is enabled") endif +# Device tree +DTB_FILE_NAME ?= stm32mp157c-ev1.dtb +FDT_SOURCES := $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(DTB_FILE_NAME))) +DTC_FLAGS += -Wno-unit_address_vs_reg + +# Macros and rules to build TF binary +STM32_TF_ELF_LDFLAGS := --hash-style=gnu --as-needed +STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME))) +STM32_TF_LINKERFILE := ${BUILD_PLAT}/stm32mp1.ld + +ASFLAGS += -DBL2_BIN_PATH=\"${BUILD_PLAT}/bl2.bin\" +ifeq ($(AARCH32_SP),sp_min) +# BL32 is built only if using SP_MIN +BL32_DEP := bl32 +ASFLAGS += -DBL32_BIN_PATH=\"${BUILD_PLAT}/bl32.bin\" +endif + +# Variables for use with stm32image +STM32IMAGEPATH ?= tools/stm32image +STM32IMAGE ?= ${STM32IMAGEPATH}/stm32image${BIN_EXT} + +# Enable flags for C files $(eval $(call assert_booleans,\ - $(sort \ - STM32MP_EMMC \ - STM32MP_SDMMC \ - STM32MP_RAW_NAND \ - STM32MP_SPI_NAND \ - STM32MP_SPI_NOR \ + $(sort \ + STM32MP_EMMC \ + STM32MP_SDMMC \ + STM32MP_RAW_NAND \ + STM32MP_SPI_NAND \ + STM32MP_SPI_NOR \ + PLAT_XLAT_TABLES_DYNAMIC \ +))) + +$(eval $(call assert_numerics,\ + $(sort \ + STM32_TF_A_COPIES \ + PLAT_PARTITION_MAX_ENTRIES \ ))) $(eval $(call add_defines,\ - $(sort \ - STM32MP_EMMC \ - STM32MP_SDMMC \ - STM32MP_RAW_NAND \ - STM32MP_SPI_NAND \ - STM32MP_SPI_NOR \ + $(sort \ + STM32MP_EMMC \ + STM32MP_SDMMC \ + STM32MP_RAW_NAND \ + STM32MP_SPI_NAND \ + STM32MP_SPI_NOR \ + PLAT_XLAT_TABLES_DYNAMIC \ + STM32_TF_A_COPIES \ + PLAT_PARTITION_MAX_ENTRIES \ ))) +# Include paths and source files PLAT_INCLUDES := -Iplat/st/common/include/ PLAT_INCLUDES += -Iplat/st/stm32mp1/include/ -# Device tree -DTB_FILE_NAME ?= stm32mp157c-ev1.dtb -FDT_SOURCES := $(addprefix fdts/, $(patsubst %.dtb,%.dts,$(DTB_FILE_NAME))) -DTC_FLAGS += -Wno-unit_address_vs_reg - include lib/libfdt/libfdt.mk PLAT_BL_COMMON_SOURCES := common/fdt_wrappers.c \ @@ -165,29 +193,17 @@ ifeq ($(AARCH32_SP),optee) BL2_SOURCES += lib/optee/optee_utils.c endif -# Macros and rules to build TF binary -STM32_TF_ELF_LDFLAGS := --hash-style=gnu --as-needed -STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME))) -STM32_TF_LINKERFILE := ${BUILD_PLAT}/stm32mp1.ld - -# Variables for use with stm32image -STM32IMAGEPATH ?= tools/stm32image -STM32IMAGE ?= ${STM32IMAGEPATH}/stm32image${BIN_EXT} - -.PHONY: check_dtc_version stm32image clean_stm32image +# Compilation rules +.PHONY: check_dtc_version stm32image clean_stm32image .SUFFIXES: -all: check_dtc_version ${STM32_TF_STM32} stm32image - -ifeq ($(AARCH32_SP),sp_min) -# BL32 is built only if using SP_MIN -BL32_DEP := bl32 -BL32_PATH := -DBL32_BIN_PATH=\"${BUILD_PLAT}/bl32.bin\" -endif +all: check_dtc_version stm32image ${STM32_TF_STM32} distclean realclean clean: clean_stm32image -stm32image: +stm32image: ${STM32IMAGE} + +${STM32IMAGE}: ${STM32IMAGE_SRC} ${Q}${MAKE} CPPFLAGS="" --no-print-directory -C ${STM32IMAGEPATH} clean_stm32image: @@ -202,32 +218,30 @@ check_dtc_version: fi -${BUILD_PLAT}/stm32mp1-%.o: ${BUILD_PLAT}/fdts/%.dtb plat/st/stm32mp1/stm32mp1.S bl2 ${BL32_DEP} - @echo " AS stm32mp1.S" - ${Q}${AS} ${ASFLAGS} ${TF_CFLAGS} \ - ${BL32_PATH} \ - -DBL2_BIN_PATH=\"${BUILD_PLAT}/bl2.bin\" \ - -DDTB_BIN_PATH=\"$<\" \ - -c plat/st/stm32mp1/stm32mp1.S -o $@ - -${STM32_TF_LINKERFILE}: plat/st/stm32mp1/stm32mp1.ld.S ${BUILD_PLAT} - @echo " LDS $<" - ${Q}${AS} ${ASFLAGS} ${TF_CFLAGS} -P -E $< -o $@ - -tf-a-%.elf: stm32mp1-%.o ${STM32_TF_LINKERFILE} - @echo " LDS $<" - ${Q}${LD} -o $@ ${STM32_TF_ELF_LDFLAGS} -Map=$(@:.elf=.map) --script ${STM32_TF_LINKERFILE} $< - -tf-a-%.bin: tf-a-%.elf - ${Q}${OC} -O binary $< $@ - @echo - @echo "Built $@ successfully" - @echo - -tf-a-%.stm32: tf-a-%.bin stm32image - @echo - @echo "Generated $@" - $(eval LOADADDR = $(shell cat $(@:.stm32=.map) | grep RAM | awk '{print $$2}')) - $(eval ENTRY = $(shell cat $(@:.stm32=.map) | grep "__BL2_IMAGE_START" | awk '{print $$1}')) - ${STM32IMAGE} -s $< -d $@ -l $(LOADADDR) -e ${ENTRY} -v ${STM32_TF_VERSION} - @echo +${BUILD_PLAT}/stm32mp1-%.o: ${BUILD_PLAT}/fdts/%.dtb plat/st/stm32mp1/stm32mp1.S bl2 ${BL32_DEP} + @echo " AS stm32mp1.S" + ${Q}${AS} ${ASFLAGS} ${TF_CFLAGS} \ + -DDTB_BIN_PATH=\"$<\" \ + -c plat/st/stm32mp1/stm32mp1.S -o $@ + +$(eval $(call MAKE_LD,${STM32_TF_LINKERFILE},plat/st/stm32mp1/stm32mp1.ld.S,2)) + +tf-a-%.elf: stm32mp1-%.o ${STM32_TF_LINKERFILE} + @echo " LDS $<" + ${Q}${LD} -o $@ ${STM32_TF_ELF_LDFLAGS} -Map=$(@:.elf=.map) --script ${STM32_TF_LINKERFILE} $< + +tf-a-%.bin: tf-a-%.elf + ${Q}${OC} -O binary $< $@ + @echo + @echo "Built $@ successfully" + @echo + +tf-a-%.stm32: ${STM32IMAGE} tf-a-%.bin + @echo + @echo "Generate $@" + $(eval LOADADDR = $(shell cat $(@:.stm32=.map) | grep RAM | awk '{print $$2}')) + $(eval ENTRY = $(shell cat $(@:.stm32=.map) | grep "__BL2_IMAGE_START" | awk '{print $$1}')) + ${Q}${STM32IMAGE} -s $(word 2,$^) -d $@ \ + -l $(LOADADDR) -e ${ENTRY} \ + -v ${STM32_TF_VERSION} + @echo diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 369ba69214..ee04a23fd9 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -37,8 +37,15 @@ #define STM32MP153A_PART_NB U(0x05000025) #define STM32MP151C_PART_NB U(0x0500002E) #define STM32MP151A_PART_NB U(0x0500002F) +#define STM32MP157F_PART_NB U(0x05000080) +#define STM32MP157D_PART_NB U(0x05000081) +#define STM32MP153F_PART_NB U(0x050000A4) +#define STM32MP153D_PART_NB U(0x050000A5) +#define STM32MP151F_PART_NB U(0x050000AE) +#define STM32MP151D_PART_NB U(0x050000AF) #define STM32MP1_REV_B U(0x2000) +#define STM32MP1_REV_Z U(0x2001) /******************************************************************************* * PACKAGE ID @@ -499,6 +506,7 @@ static inline uint32_t tamp_bkpr(uint32_t idx) /******************************************************************************* * Miscellaneous STM32MP1 peripherals base address ******************************************************************************/ +#define BSEC_BASE U(0x5C005000) #define CRYP1_BASE U(0x54001000) #define DBGMCU_BASE U(0x50081000) #define HASH1_BASE U(0x54002000) @@ -507,6 +515,8 @@ static inline uint32_t tamp_bkpr(uint32_t idx) #define RNG1_BASE U(0x54003000) #define RTC_BASE U(0x5c004000) #define SPI6_BASE U(0x5c001000) +#define STGEN_BASE U(0x5c008000) +#define SYSCFG_BASE U(0x50020000) /******************************************************************************* * Device Tree defines @@ -515,6 +525,5 @@ static inline uint32_t tamp_bkpr(uint32_t idx) #define DT_IWDG_COMPAT "st,stm32mp1-iwdg" #define DT_PWR_COMPAT "st,stm32mp1,pwr-reg" #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" -#define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg" #endif /* STM32MP1_DEF_H */ diff --git a/plat/st/stm32mp1/stm32mp1_helper.S b/plat/st/stm32mp1/stm32mp1_helper.S index 407eb39797..3021362365 100644 --- a/plat/st/stm32mp1/stm32mp1_helper.S +++ b/plat/st/stm32mp1/stm32mp1_helper.S @@ -198,7 +198,7 @@ func plat_crash_console_init endfunc plat_crash_console_init /* --------------------------------------------- - * int plat_crash_console_flush(void) + * void plat_crash_console_flush(void) * * Flush the crash console without a C Runtime stack. * --------------------------------------------- diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c index fd60db282b..bc77ee3342 100644 --- a/plat/st/stm32mp1/stm32mp1_private.c +++ b/plat/st/stm32mp1/stm32mp1_private.c @@ -16,18 +16,22 @@ /* Internal layout of the 32bit OTP word board_id */ #define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16) #define BOARD_ID_BOARD_NB_SHIFT 16 -#define BOARD_ID_VARIANT_MASK GENMASK(15, 12) -#define BOARD_ID_VARIANT_SHIFT 12 +#define BOARD_ID_VARCPN_MASK GENMASK(15, 12) +#define BOARD_ID_VARCPN_SHIFT 12 #define BOARD_ID_REVISION_MASK GENMASK(11, 8) #define BOARD_ID_REVISION_SHIFT 8 +#define BOARD_ID_VARFG_MASK GENMASK(7, 4) +#define BOARD_ID_VARFG_SHIFT 4 #define BOARD_ID_BOM_MASK GENMASK(3, 0) #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ BOARD_ID_BOARD_NB_SHIFT) -#define BOARD_ID2VAR(_id) (((_id) & BOARD_ID_VARIANT_MASK) >> \ - BOARD_ID_VARIANT_SHIFT) +#define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \ + BOARD_ID_VARCPN_SHIFT) #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ BOARD_ID_REVISION_SHIFT) +#define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \ + BOARD_ID_VARFG_SHIFT) #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) #if defined(IMAGE_BL2) @@ -154,6 +158,8 @@ static int get_part_number(uint32_t *part_nb) uint32_t part_number; uint32_t dev_id; + assert(part_nb != NULL); + if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) { return -1; } @@ -175,6 +181,8 @@ static int get_cpu_package(uint32_t *cpu_package) { uint32_t package; + assert(cpu_package != NULL); + if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) { ERROR("BSEC: PACKAGE_OTP Error\n"); return -1; @@ -220,6 +228,24 @@ void stm32mp_print_cpuinfo(void) case STM32MP151A_PART_NB: cpu_s = "151A"; break; + case STM32MP157F_PART_NB: + cpu_s = "157F"; + break; + case STM32MP157D_PART_NB: + cpu_s = "157D"; + break; + case STM32MP153F_PART_NB: + cpu_s = "153F"; + break; + case STM32MP153D_PART_NB: + cpu_s = "153D"; + break; + case STM32MP151F_PART_NB: + cpu_s = "151F"; + break; + case STM32MP151D_PART_NB: + cpu_s = "151D"; + break; default: cpu_s = "????"; break; @@ -261,6 +287,9 @@ void stm32mp_print_cpuinfo(void) case STM32MP1_REV_B: cpu_r = "B"; break; + case STM32MP1_REV_Z: + cpu_r = "Z"; + break; default: cpu_r = "?"; break; @@ -308,9 +337,10 @@ void stm32mp_print_boardinfo(void) rev[0] = BOARD_ID2REV(board_id) - 1 + 'A'; rev[1] = '\0'; - NOTICE("Board: MB%04x Var%d Rev.%s-%02d\n", + NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n", BOARD_ID2NB(board_id), - BOARD_ID2VAR(board_id), + BOARD_ID2VARCPN(board_id), + BOARD_ID2VARFG(board_id), rev, BOARD_ID2BOM(board_id)); } @@ -320,7 +350,6 @@ void stm32mp_print_boardinfo(void) bool stm32mp_is_single_core(void) { uint32_t part_number; - bool ret = false; if (get_part_number(&part_number) < 0) { ERROR("Invalid part number, assume single core chip"); @@ -330,14 +359,13 @@ bool stm32mp_is_single_core(void) switch (part_number) { case STM32MP151A_PART_NB: case STM32MP151C_PART_NB: - ret = true; - break; + case STM32MP151D_PART_NB: + case STM32MP151F_PART_NB: + return true; default: - break; + return false; } - - return ret; } /* Return true when device is in closed state */ diff --git a/plat/st/stm32mp1/stm32mp1_syscfg.c b/plat/st/stm32mp1/stm32mp1_syscfg.c index 2fd06f38a3..109725c8ac 100644 --- a/plat/st/stm32mp1/stm32mp1_syscfg.c +++ b/plat/st/stm32mp1/stm32mp1_syscfg.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, STMicroelectronics - All Rights Reserved + * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: BSD-3-Clause */ @@ -63,18 +63,17 @@ void stm32mp1_syscfg_init(void) uint32_t bootr; uint32_t otp = 0; uint32_t vdd_voltage; - uintptr_t syscfg_base = dt_get_syscfg_base(); /* * Interconnect update : select master using the port 1. * LTDC = AXI_M9. */ - mmio_write_32(syscfg_base + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9); + mmio_write_32(SYSCFG_BASE + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9); /* Disable Pull-Down for boot pin connected to VDD */ - bootr = mmio_read_32(syscfg_base + SYSCFG_BOOTR) & + bootr = mmio_read_32(SYSCFG_BASE + SYSCFG_BOOTR) & SYSCFG_BOOTR_BOOT_MASK; - mmio_clrsetbits_32(syscfg_base + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK, + mmio_clrsetbits_32(SYSCFG_BASE + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK, bootr << SYSCFG_BOOTR_BOOTPD_SHIFT); /* @@ -105,7 +104,7 @@ void stm32mp1_syscfg_init(void) if (vdd_voltage == 0U) { WARN("VDD unknown"); } else if (vdd_voltage < 2700000U) { - mmio_write_32(syscfg_base + SYSCFG_IOCTRLSETR, + mmio_write_32(SYSCFG_BASE + SYSCFG_IOCTRLSETR, SYSCFG_IOCTRLSETR_HSLVEN_TRACE | SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI | SYSCFG_IOCTRLSETR_HSLVEN_ETH | @@ -129,8 +128,6 @@ void stm32mp1_syscfg_init(void) void stm32mp1_syscfg_enable_io_compensation(void) { - uintptr_t syscfg_base = dt_get_syscfg_base(); - /* * Activate automatic I/O compensation. * Warning: need to ensure CSI enabled and ready in clock driver. @@ -138,20 +135,19 @@ void stm32mp1_syscfg_enable_io_compensation(void) */ stm32mp1_clk_enable_non_secure(SYSCFG); - mmio_setbits_32(syscfg_base + SYSCFG_CMPENSETR, + mmio_setbits_32(SYSCFG_BASE + SYSCFG_CMPENSETR, SYSCFG_CMPENSETR_MPU_EN); - while ((mmio_read_32(syscfg_base + SYSCFG_CMPCR) & + while ((mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY) == 0U) { ; } - mmio_clrbits_32(syscfg_base + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); + mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); } void stm32mp1_syscfg_disable_io_compensation(void) { - uintptr_t syscfg_base = dt_get_syscfg_base(); uint32_t value; /* @@ -160,20 +156,18 @@ void stm32mp1_syscfg_disable_io_compensation(void) * requested for other usages and always OFF in STANDBY. * Disable non-secure SYSCFG clock, we assume non-secure is suspended. */ - value = mmio_read_32(syscfg_base + SYSCFG_CMPCR) >> + value = mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) >> SYSCFG_CMPCR_ANSRC_SHIFT; - mmio_clrbits_32(syscfg_base + SYSCFG_CMPCR, + mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_RANSRC | SYSCFG_CMPCR_RAPSRC); - value = mmio_read_32(syscfg_base + SYSCFG_CMPCR) | + value = mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) | (value << SYSCFG_CMPCR_RANSRC_SHIFT); - mmio_write_32(syscfg_base + SYSCFG_CMPCR, value); - - mmio_setbits_32(syscfg_base + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); + mmio_write_32(SYSCFG_BASE + SYSCFG_CMPCR, value | SYSCFG_CMPCR_SW_CTRL); - mmio_clrbits_32(syscfg_base + SYSCFG_CMPENSETR, + mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPENSETR, SYSCFG_CMPENSETR_MPU_EN); stm32mp1_clk_disable_non_secure(SYSCFG); diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/k3/common/k3_helpers.S index 3afca591ec..f4f7d18eac 100644 --- a/plat/ti/k3/common/k3_helpers.S +++ b/plat/ti/k3/common/k3_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -141,10 +141,10 @@ func plat_crash_console_putc endfunc plat_crash_console_putc /* --------------------------------------------- - * int plat_crash_console_flush() + * void plat_crash_console_flush() * Function to force a write of all buffered * data that hasn't been output. - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : x0, x1 * --------------------------------------------- */ diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S b/plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S index beba664058..7eab337e94 100644 --- a/plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S +++ b/plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -106,10 +106,10 @@ func plat_crash_console_putc endfunc plat_crash_console_putc /* --------------------------------------------- - * int plat_crash_console_flush() + * void plat_crash_console_flush() * Function to force a write of all buffered * data that hasn't been output. - * Out : return -1 on error else return 0. + * Out : void. * Clobber list : r0 * --------------------------------------------- */ |