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author | Chandni Cherukuri <chandni.cherukuri@arm.com> | 2019-02-22 13:41:03 +0530 |
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committer | Chandni Cherukuri <chandni.cherukuri@arm.com> | 2019-02-27 12:31:36 +0530 |
commit | f717eca9e5a169b7f4a7a68200d2b6d74baf1a17 (patch) | |
tree | 948b3009a433ed8de5447b942ea8cb887ede02f6 /plat | |
parent | ab3d22473df279c61ed4d4873d26b072dcf887e8 (diff) | |
download | trusted-firmware-a-f717eca9e5a169b7f4a7a68200d2b6d74baf1a17.tar.gz |
board/rdn1edge: rename sgiclarka to rdn1edge
Replace all usage of 'sgiclark' with 'rdn1e1edge' and 'sgiclarka' with
'rdn1edge' as per the updated product names.
Change-Id: Idbc157c73477ec32f507ba2d4a4e907d8813374c
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Diffstat (limited to 'plat')
-rw-r--r-- | plat/arm/board/rdn1edge/fdts/rdn1edge_nt_fw_config.dts (renamed from plat/arm/board/sgiclarka/fdts/sgiclarka_nt_fw_config.dts) | 4 | ||||
-rw-r--r-- | plat/arm/board/rdn1edge/fdts/rdn1edge_tb_fw_config.dts (renamed from plat/arm/board/sgiclarka/fdts/sgiclarka_tb_fw_config.dts) | 0 | ||||
-rw-r--r-- | plat/arm/board/rdn1edge/include/platform_def.h (renamed from plat/arm/board/sgiclarka/include/platform_def.h) | 6 | ||||
-rw-r--r-- | plat/arm/board/rdn1edge/platform.mk (renamed from plat/arm/board/sgiclarka/platform.mk) | 14 | ||||
-rw-r--r-- | plat/arm/board/rdn1edge/rdn1edge_plat.c (renamed from plat/arm/board/sgiclarka/sgiclarka_plat.c) | 0 | ||||
-rw-r--r-- | plat/arm/board/rdn1edge/rdn1edge_security.c | 40 | ||||
-rw-r--r-- | plat/arm/board/sgiclarka/sgiclarka_security.c | 40 |
7 files changed, 52 insertions, 52 deletions
diff --git a/plat/arm/board/sgiclarka/fdts/sgiclarka_nt_fw_config.dts b/plat/arm/board/rdn1edge/fdts/rdn1edge_nt_fw_config.dts index 43bd85692b..fff5874769 100644 --- a/plat/arm/board/sgiclarka/fdts/sgiclarka_nt_fw_config.dts +++ b/plat/arm/board/rdn1edge/fdts/rdn1edge_nt_fw_config.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,7 +7,7 @@ /dts-v1/; / { /* compatible string */ - compatible = "arm,sgi-clark"; + compatible = "arm,rd-n1edge"; /* * Place holder for system-id node with default values. The diff --git a/plat/arm/board/sgiclarka/fdts/sgiclarka_tb_fw_config.dts b/plat/arm/board/rdn1edge/fdts/rdn1edge_tb_fw_config.dts index b14d7adca9..b14d7adca9 100644 --- a/plat/arm/board/sgiclarka/fdts/sgiclarka_tb_fw_config.dts +++ b/plat/arm/board/rdn1edge/fdts/rdn1edge_tb_fw_config.dts diff --git a/plat/arm/board/sgiclarka/include/platform_def.h b/plat/arm/board/rdn1edge/include/platform_def.h index d2cdb49744..2ca0dd4ec8 100644 --- a/plat/arm/board/sgiclarka/include/platform_def.h +++ b/plat/arm/board/rdn1edge/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,8 +18,8 @@ #define PLAT_CSS_MHU_BASE UL(0x45400000) /* Base address of DMC-620 instances */ -#define SGICLARKA_DMC620_BASE0 UL(0x4e000000) -#define SGICLARKA_DMC620_BASE1 UL(0x4e100000) +#define RDN1EDGE_DMC620_BASE0 UL(0x4e000000) +#define RDN1EDGE_DMC620_BASE1 UL(0x4e100000) /* System power domain level */ #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 diff --git a/plat/arm/board/sgiclarka/platform.mk b/plat/arm/board/rdn1edge/platform.mk index 81e416efce..cacdaa13c2 100644 --- a/plat/arm/board/sgiclarka/platform.mk +++ b/plat/arm/board/rdn1edge/platform.mk @@ -6,34 +6,34 @@ include plat/arm/css/sgi/sgi-common.mk -SGICLARKA_BASE = plat/arm/board/sgiclarka +RDN1EDGE_BASE = plat/arm/board/rdn1edge -PLAT_INCLUDES += -I${SGICLARKA_BASE}/include/ +PLAT_INCLUDES += -I${RDN1EDGE_BASE}/include/ SGI_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S BL1_SOURCES += ${SGI_CPU_SOURCES} -BL2_SOURCES += ${SGICLARKA_BASE}/sgiclarka_plat.c \ - ${SGICLARKA_BASE}/sgiclarka_security.c \ +BL2_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_plat.c \ + ${RDN1EDGE_BASE}/rdn1edge_security.c \ drivers/arm/tzc/tzc_dmc620.c \ lib/utils/mem_region.c \ plat/arm/common/arm_nor_psci_mem_protect.c BL31_SOURCES += ${SGI_CPU_SOURCES} \ - ${SGICLARKA_BASE}/sgiclarka_plat.c \ + ${RDN1EDGE_BASE}/rdn1edge_plat.c \ drivers/cfi/v2m/v2m_flash.c \ lib/utils/mem_region.c \ plat/arm/common/arm_nor_psci_mem_protect.c # Add the FDT_SOURCES and options for Dynamic Config -FDT_SOURCES += ${SGICLARKA_BASE}/fdts/${PLAT}_tb_fw_config.dts +FDT_SOURCES += ${RDN1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb # Add the TB_FW_CONFIG to FIP and specify the same to certtool $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config)) -FDT_SOURCES += ${SGICLARKA_BASE}/fdts/${PLAT}_nt_fw_config.dts +FDT_SOURCES += ${RDN1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb # Add the NT_FW_CONFIG to FIP and specify the same to certtool diff --git a/plat/arm/board/sgiclarka/sgiclarka_plat.c b/plat/arm/board/rdn1edge/rdn1edge_plat.c index 3b7e5ee4e4..3b7e5ee4e4 100644 --- a/plat/arm/board/sgiclarka/sgiclarka_plat.c +++ b/plat/arm/board/rdn1edge/rdn1edge_plat.c diff --git a/plat/arm/board/rdn1edge/rdn1edge_security.c b/plat/arm/board/rdn1edge/rdn1edge_security.c new file mode 100644 index 0000000000..ffa8935246 --- /dev/null +++ b/plat/arm/board/rdn1edge/rdn1edge_security.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2019, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <platform_def.h> + +#include <common/debug.h> +#include <drivers/arm/tzc_dmc620.h> + +uintptr_t rdn1edge_dmc_base[] = { + RDN1EDGE_DMC620_BASE0, + RDN1EDGE_DMC620_BASE1 +}; + +static const tzc_dmc620_driver_data_t rdn1edge_plat_driver_data = { + .dmc_base = rdn1edge_dmc_base, + .dmc_count = ARRAY_SIZE(rdn1edge_dmc_base) +}; + +static const tzc_dmc620_acc_addr_data_t rdn1edge_acc_addr_data[] = { + { + .region_base = ARM_AP_TZC_DRAM1_BASE, + .region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1, + .sec_attr = TZC_DMC620_REGION_S_RDWR + } +}; + +static const tzc_dmc620_config_data_t rdn1edge_plat_config_data = { + .plat_drv_data = &rdn1edge_plat_driver_data, + .plat_acc_addr_data = rdn1edge_acc_addr_data, + .acc_addr_count = ARRAY_SIZE(rdn1edge_acc_addr_data) +}; + +/* Initialize the secure environment */ +void plat_arm_security_setup(void) +{ + arm_tzc_dmc620_setup(&rdn1edge_plat_config_data); +} diff --git a/plat/arm/board/sgiclarka/sgiclarka_security.c b/plat/arm/board/sgiclarka/sgiclarka_security.c deleted file mode 100644 index c455111d10..0000000000 --- a/plat/arm/board/sgiclarka/sgiclarka_security.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <platform_def.h> - -#include <common/debug.h> -#include <drivers/arm/tzc_dmc620.h> - -uintptr_t sgiclarka_dmc_base[] = { - SGICLARKA_DMC620_BASE0, - SGICLARKA_DMC620_BASE1 -}; - -static const tzc_dmc620_driver_data_t sgiclarka_plat_driver_data = { - .dmc_base = sgiclarka_dmc_base, - .dmc_count = ARRAY_SIZE(sgiclarka_dmc_base) -}; - -static const tzc_dmc620_acc_addr_data_t sgiclarka_acc_addr_data[] = { - { - .region_base = ARM_AP_TZC_DRAM1_BASE, - .region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1, - .sec_attr = TZC_DMC620_REGION_S_RDWR - } -}; - -static const tzc_dmc620_config_data_t sgiclarka_plat_config_data = { - .plat_drv_data = &sgiclarka_plat_driver_data, - .plat_acc_addr_data = sgiclarka_acc_addr_data, - .acc_addr_count = ARRAY_SIZE(sgiclarka_acc_addr_data) -}; - -/* Initialize the secure environment */ -void plat_arm_security_setup(void) -{ - arm_tzc_dmc620_setup(&sgiclarka_plat_config_data); -} |