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authorGuo Yi <yguo@cavium.com>2021-02-17 00:56:48 +0000
committerManish Pandey <manish.pandey2@arm.com>2021-04-20 12:59:54 +0200
commited1587d0257361cd9f78a134012df394bfe5eb63 (patch)
tree0eb19d353e0bf2664cbb6b1a8ebfd0ffbb1af114 /plat
parent718dbcac9c36c51a1527ed298fba6fa5ee88632f (diff)
downloadtrusted-firmware-a-ed1587d0257361cd9f78a134012df394bfe5eb63.tar.gz
plat: marvell: armada: a8k: Fix LD selector mask
Fixed a bug that the actually bit number was used as a mask to select LD0 or LD1 fuse Signed-off-by: Guo Yi <yguo@cavium.com> Change-Id: I4bec268c3dc2566350b4a73f655bce222707e25b Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46146 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Diffstat (limited to 'plat')
-rw-r--r--plat/marvell/armada/a8k/common/plat_ble_setup.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/plat/marvell/armada/a8k/common/plat_ble_setup.c b/plat/marvell/armada/a8k/common/plat_ble_setup.c
index 41143276a3..59a3a3ae1a 100644
--- a/plat/marvell/armada/a8k/common/plat_ble_setup.c
+++ b/plat/marvell/armada/a8k/common/plat_ble_setup.c
@@ -383,7 +383,7 @@ static void ble_plat_svc_config(void)
/* Set access to LD0 */
reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG);
- reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_OFFS;
+ reg_val &= ~EFUSE_SRV_CTRL_LD_SEL_USER_MASK;
mmio_write_32(MVEBU_AP_EFUSE_SRV_CTRL_REG, reg_val);
/* Obtain the value of LD0[125:63] */