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authorSoby Mathew <soby.mathew@arm.com>2014-06-06 10:18:52 +0100
committerSoby Mathew <soby.mathew@arm.com>2014-06-18 13:37:34 +0100
commitb1e71b20d8061abff4496a8ce81d121bac1c3b10 (patch)
tree98e6f567ba46eb6cca490fcbe23c8cf8b8030d54 /plat
parent977fbcd4e0842e590a961d6f40c14653caa9301a (diff)
downloadtrusted-firmware-a-b1e71b20d8061abff4496a8ce81d121bac1c3b10.tar.gz
Remove re-initialisation of system timers after warm boot for FVP
This patch removes the reinitialisation of memory mapped system timer registers after a warm boot for the FVP. The system timers in FVP are in the 'Always ON' power domain which meant the reinitialisation was redundant and it could have conflicted with the setup the normal world has done. The programming of CNTACR(x) and CNTNSAR, the system timer registers, are removed from the warm boot path with this patch. Fixes ARM-software/tf-issues#169 Change-Id: Ie982eb03d1836b15ef3cf1568de2ea68a08b443e
Diffstat (limited to 'plat')
-rw-r--r--plat/fvp/fvp_pm.c13
1 files changed, 1 insertions, 12 deletions
diff --git a/plat/fvp/fvp_pm.c b/plat/fvp/fvp_pm.c
index d70264304a..03f06e7c60 100644
--- a/plat/fvp/fvp_pm.c
+++ b/plat/fvp/fvp_pm.c
@@ -290,7 +290,7 @@ int fvp_affinst_on_finish(unsigned long mpidr,
int rc = PSCI_E_SUCCESS;
unsigned long linear_id, cpu_setup;
mailbox_t *fvp_mboxes;
- unsigned int gicd_base, gicc_base, reg_val, ectlr;
+ unsigned int gicd_base, gicc_base, ectlr;
switch (afflvl) {
@@ -354,17 +354,6 @@ int fvp_affinst_on_finish(unsigned long mpidr,
/* TODO: This setup is needed only after a cold boot */
gic_pcpu_distif_setup(gicd_base);
- /* Allow access to the System counter timer module */
- reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
- reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);
- reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT);
- mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val);
- mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val);
-
- reg_val = (1 << CNTNSAR_NS_SHIFT(0)) |
- (1 << CNTNSAR_NS_SHIFT(1));
- mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val);
-
break;
default: