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authorYann Gautier <yann.gautier@st.com>2019-02-14 11:01:20 +0100
committerYann Gautier <yann.gautier@st.com>2019-02-14 11:20:23 +0100
commit7ae58c6ba79fee3cc032aae2105b073304409ebc (patch)
tree285ded01264f6dc644bd7adda5736e9b9da448af /plat
parent447b2b137d7286a1ef451336c6e73fb7fd8999a1 (diff)
downloadtrusted-firmware-a-7ae58c6ba79fee3cc032aae2105b073304409ebc.tar.gz
stm32mp1: use functions to retrieve some peripheral addresses
PWR, RCC, DDRPHYC & DDRCTRL addresses can be retrieved from device tree. Platform asserts the value read from the DT are the SoC addresses. Change-Id: I43f0890b51918a30c87ac067d3780ab27a0f59de Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Nicolas LE BAYON <nicolas.le.bayon@st.com>
Diffstat (limited to 'plat')
-rw-r--r--plat/st/common/include/stm32mp_common.h12
-rw-r--r--plat/st/common/include/stm32mp_dt.h3
-rw-r--r--plat/st/common/stm32mp_common.c53
-rw-r--r--plat/st/common/stm32mp_dt.c67
-rw-r--r--plat/st/stm32mp1/bl2_plat_setup.c19
-rw-r--r--plat/st/stm32mp1/stm32mp1_def.h1
-rw-r--r--plat/st/stm32mp1/stm32mp1_pm.c3
7 files changed, 150 insertions, 8 deletions
diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h
index 5f54b103de..fa0b63031f 100644
--- a/plat/st/common/include/stm32mp_common.h
+++ b/plat/st/common/include/stm32mp_common.h
@@ -16,6 +16,18 @@
void stm32mp_save_boot_ctx_address(uintptr_t address);
uintptr_t stm32mp_get_boot_ctx_address(void);
+/* Return the base address of the DDR controller */
+uintptr_t stm32mp_ddrctrl_base(void);
+
+/* Return the base address of the DDR PHY */
+uintptr_t stm32mp_ddrphyc_base(void);
+
+/* Return the base address of the PWR peripheral */
+uintptr_t stm32mp_pwr_base(void);
+
+/* Return the base address of the RCC peripheral */
+uintptr_t stm32mp_rcc_base(void);
+
/*
* Platform util functions for the GPIO driver
* @bank: Target GPIO bank ID as per DT bindings
diff --git a/plat/st/common/include/stm32mp_dt.h b/plat/st/common/include/stm32mp_dt.h
index 56357dbff1..3415b051d5 100644
--- a/plat/st/common/include/stm32mp_dt.h
+++ b/plat/st/common/include/stm32mp_dt.h
@@ -38,6 +38,9 @@ int dt_get_node(struct dt_node_info *info, int offset, const char *compat);
int dt_get_stdout_uart_info(struct dt_node_info *info);
int dt_get_stdout_node_offset(void);
uint32_t dt_get_ddr_size(void);
+uintptr_t dt_get_ddrctrl_base(void);
+uintptr_t dt_get_ddrphyc_base(void);
+uintptr_t dt_get_pwr_base(void);
const char *dt_get_board_model(void);
#endif /* STM32MP_DT_H */
diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c
index aecef4718b..2aba41e54f 100644
--- a/plat/st/common/stm32mp_common.c
+++ b/plat/st/common/stm32mp_common.c
@@ -10,6 +10,7 @@
#include <arch_helpers.h>
#include <common/debug.h>
+#include <drivers/st/stm32mp_clkfunc.h>
#include <plat/common/platform.h>
uintptr_t plat_get_ns_image_entrypoint(void)
@@ -34,6 +35,58 @@ uintptr_t stm32mp_get_boot_ctx_address(void)
return boot_ctx_address;
}
+uintptr_t stm32mp_ddrctrl_base(void)
+{
+ static uintptr_t ddrctrl_base;
+
+ if (ddrctrl_base == 0) {
+ ddrctrl_base = dt_get_ddrctrl_base();
+
+ assert(ddrctrl_base == DDRCTRL_BASE);
+ }
+
+ return ddrctrl_base;
+}
+
+uintptr_t stm32mp_ddrphyc_base(void)
+{
+ static uintptr_t ddrphyc_base;
+
+ if (ddrphyc_base == 0) {
+ ddrphyc_base = dt_get_ddrphyc_base();
+
+ assert(ddrphyc_base == DDRPHYC_BASE);
+ }
+
+ return ddrphyc_base;
+}
+
+uintptr_t stm32mp_pwr_base(void)
+{
+ static uintptr_t pwr_base;
+
+ if (pwr_base == 0) {
+ pwr_base = dt_get_pwr_base();
+
+ assert(pwr_base == PWR_BASE);
+ }
+
+ return pwr_base;
+}
+
+uintptr_t stm32mp_rcc_base(void)
+{
+ static uintptr_t rcc_base;
+
+ if (rcc_base == 0) {
+ rcc_base = fdt_rcc_read_addr();
+
+ assert(rcc_base == RCC_BASE);
+ }
+
+ return rcc_base;
+}
+
uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
{
if (bank == GPIO_BANK_Z) {
diff --git a/plat/st/common/stm32mp_dt.c b/plat/st/common/stm32mp_dt.c
index c0b0518d9c..e64433bc82 100644
--- a/plat/st/common/stm32mp_dt.c
+++ b/plat/st/common/stm32mp_dt.c
@@ -292,6 +292,73 @@ uint32_t dt_get_ddr_size(void)
}
/*******************************************************************************
+ * This function gets DDRCTRL base address information from the DT.
+ * Returns value on success, and 0 on failure.
+ ******************************************************************************/
+uintptr_t dt_get_ddrctrl_base(void)
+{
+ int node;
+ uint32_t array[4];
+
+ node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT);
+ if (node < 0) {
+ INFO("%s: Cannot read DDR node in DT\n", __func__);
+ return 0;
+ }
+
+ if (fdt_read_uint32_array(node, "reg", array, 4) < 0) {
+ return 0;
+ }
+
+ return array[0];
+}
+
+/*******************************************************************************
+ * This function gets DDRPHYC base address information from the DT.
+ * Returns value on success, and 0 on failure.
+ ******************************************************************************/
+uintptr_t dt_get_ddrphyc_base(void)
+{
+ int node;
+ uint32_t array[4];
+
+ node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT);
+ if (node < 0) {
+ INFO("%s: Cannot read DDR node in DT\n", __func__);
+ return 0;
+ }
+
+ if (fdt_read_uint32_array(node, "reg", array, 4) < 0) {
+ return 0;
+ }
+
+ return array[2];
+}
+
+/*******************************************************************************
+ * This function gets PWR base address information from the DT.
+ * Returns value on success, and 0 on failure.
+ ******************************************************************************/
+uintptr_t dt_get_pwr_base(void)
+{
+ int node;
+ const fdt32_t *cuint;
+
+ node = fdt_node_offset_by_compatible(fdt, -1, DT_PWR_COMPAT);
+ if (node < 0) {
+ INFO("%s: Cannot read PWR node in DT\n", __func__);
+ return 0;
+ }
+
+ cuint = fdt_getprop(fdt, node, "reg", NULL);
+ if (cuint == NULL) {
+ return 0;
+ }
+
+ return fdt32_to_cpu(*cuint);
+}
+
+/*******************************************************************************
* This function retrieves board model from DT
* Returns string taken from model node, NULL otherwise
******************************************************************************/
diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index 69dc3fb107..5ab20845c7 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -31,7 +31,7 @@ static struct console_stm32 console;
static void print_reset_reason(void)
{
- uint32_t rstsr = mmio_read_32(RCC_BASE + RCC_MP_RSTSCLRR);
+ uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR);
if (rstsr == 0U) {
WARN("Reset reason unknown\n");
@@ -147,6 +147,8 @@ void bl2_el3_plat_arch_setup(void)
boot_api_context_t *boot_context =
(boot_api_context_t *)stm32mp_get_boot_ctx_address();
uint32_t clk_rate;
+ uintptr_t pwr_base;
+ uintptr_t rcc_base;
mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
BL_CODE_END - BL_CODE_BASE,
@@ -174,27 +176,30 @@ void bl2_el3_plat_arch_setup(void)
panic();
}
+ pwr_base = stm32mp_pwr_base();
+ rcc_base = stm32mp_rcc_base();
+
/*
* Disable the backup domain write protection.
* The protection is enable at each reset by hardware
* and must be disabled by software.
*/
- mmio_setbits_32(PWR_BASE + PWR_CR1, PWR_CR1_DBP);
+ mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP);
- while ((mmio_read_32(PWR_BASE + PWR_CR1) & PWR_CR1_DBP) == 0U) {
+ while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) {
;
}
/* Reset backup domain on cold boot cases */
- if ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) {
- mmio_setbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST);
+ if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) {
+ mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
- while ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_VSWRST) ==
+ while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) ==
0U) {
;
}
- mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST);
+ mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
}
generic_delay_timer_init();
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index beb588c7ff..8d7cea327b 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -253,6 +253,7 @@ static inline uint32_t tamp_bkpr(uint32_t idx)
/*******************************************************************************
* Device Tree defines
******************************************************************************/
+#define DT_PWR_COMPAT "st,stm32mp1-pwr"
#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
#endif /* STM32MP1_DEF_H */
diff --git a/plat/st/stm32mp1/stm32mp1_pm.c b/plat/st/stm32mp1/stm32mp1_pm.c
index c4d0232711..3262607a5e 100644
--- a/plat/st/stm32mp1/stm32mp1_pm.c
+++ b/plat/st/stm32mp1/stm32mp1_pm.c
@@ -159,7 +159,8 @@ static void __dead2 stm32_system_off(void)
static void __dead2 stm32_system_reset(void)
{
- mmio_setbits_32(RCC_BASE + RCC_MP_GRSTCSETR, RCC_MP_GRSTCSETR_MPSYSRST);
+ mmio_setbits_32(stm32mp_rcc_base() + RCC_MP_GRSTCSETR,
+ RCC_MP_GRSTCSETR_MPSYSRST);
/* Loop in case system reset is not immediately caught */
for ( ; ; ) {