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author | Jiafei Pan <Jiafei.Pan@nxp.com> | 2021-07-20 17:14:32 +0800 |
---|---|---|
committer | Jiafei Pan <Jiafei.Pan@nxp.com> | 2021-08-26 10:08:57 +0800 |
commit | 08695df91dffb2e45c01866b760d73cb531a071b (patch) | |
tree | f17134b90bc1ce22e0829b32857019bc64b12d6b /plat | |
parent | 1ca72295290a11164657da66e014ba690e05bc1e (diff) | |
download | trusted-firmware-a-08695df91dffb2e45c01866b760d73cb531a071b.tar.gz |
refactor(plat/nxp): refine api to read SVR register
1. Refined struct soc_info_t definition.
2. Refined get_soc_info function.
3. Fixed some SVR persernality value.
4. Refined API to get cluster numbers and cores per cluster.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I3c20611a523516cc63330dce4c925e6cda1e93c4
Diffstat (limited to 'plat')
-rw-r--r-- | plat/nxp/common/setup/include/plat_common.h | 15 | ||||
-rw-r--r-- | plat/nxp/common/setup/ls_common.c | 26 | ||||
-rw-r--r-- | plat/nxp/soc-lx2160a/include/soc.h | 11 | ||||
-rw-r--r-- | plat/nxp/soc-lx2160a/soc.c | 35 |
4 files changed, 48 insertions, 39 deletions
diff --git a/plat/nxp/common/setup/include/plat_common.h b/plat/nxp/common/setup/include/plat_common.h index 18d36ca262..97a9cb7f56 100644 --- a/plat/nxp/common/setup/include/plat_common.h +++ b/plat/nxp/common/setup/include/plat_common.h @@ -1,5 +1,5 @@ /* - * Copyright 2018-2020 NXP + * Copyright 2018-2021 NXP * * SPDX-License-Identifier: BSD-3-Clause * @@ -10,7 +10,9 @@ #include <stdbool.h> +#include <dcfg.h> #include <lib/el3_runtime/cpu_data.h> + #include <platform_def.h> #ifdef IMAGE_BL31 @@ -129,18 +131,19 @@ void ls_setup_page_tables(uintptr_t total_base, #endif ); - /* Structure to define SoC personality */ struct soc_type { char name[10]; - uint32_t personality; - uint32_t num_clusters; - uint32_t cores_per_cluster; + uint32_t version; + uint8_t num_clusters; + uint8_t cores_per_cluster; }; +void get_cluster_info(const struct soc_type *soc_list, uint8_t ps_count, + uint8_t *num_clusters, uint8_t *cores_per_cluster); #define SOC_ENTRY(n, v, ncl, nc) { \ .name = #n, \ - .personality = SVR_##v, \ + .version = SVR_##v, \ .num_clusters = (ncl), \ .cores_per_cluster = (nc)} diff --git a/plat/nxp/common/setup/ls_common.c b/plat/nxp/common/setup/ls_common.c index a6946e1a85..e7ae060825 100644 --- a/plat/nxp/common/setup/ls_common.c +++ b/plat/nxp/common/setup/ls_common.c @@ -1,5 +1,5 @@ /* - * Copyright 2018-2020 NXP + * Copyright 2018-2021 NXP * * SPDX-License-Identifier: BSD-3-Clause * @@ -238,3 +238,27 @@ const mmap_region_t *plat_ls_get_mmap(void) { return plat_ls_mmap; } + +/* + * This function get the number of clusters and cores count per cluster + * in the SoC. + */ +void get_cluster_info(const struct soc_type *soc_list, uint8_t ps_count, + uint8_t *num_clusters, uint8_t *cores_per_cluster) +{ + const soc_info_t *soc_info = get_soc_info(); + *num_clusters = NUMBER_OF_CLUSTERS; + *cores_per_cluster = CORES_PER_CLUSTER; + unsigned int i; + + for (i = 0U; i < ps_count; i++) { + if (soc_list[i].version == soc_info->svr_reg.bf_ver.version) { + *num_clusters = soc_list[i].num_clusters; + *cores_per_cluster = soc_list[i].cores_per_cluster; + break; + } + } + + VERBOSE("NUM of cluster = 0x%x, Cores per cluster = 0x%x\n", + *num_clusters, *cores_per_cluster); +} diff --git a/plat/nxp/soc-lx2160a/include/soc.h b/plat/nxp/soc-lx2160a/include/soc.h index bd236201ce..7cc4a03eba 100644 --- a/plat/nxp/soc-lx2160a/include/soc.h +++ b/plat/nxp/soc-lx2160a/include/soc.h @@ -1,5 +1,5 @@ /* - * Copyright 2018-2020 NXP + * Copyright 2018-2021 NXP * * SPDX-License-Identifier: BSD-3-Clause * @@ -52,11 +52,10 @@ #define FLEXSPI_NOR 0xf /* End: Macros used by soc.c: get_boot_dev */ -/* bits */ -/* SVR Definition */ -#define SVR_LX2160A 0x04 -#define SVR_LX2120A 0x14 -#define SVR_LX2080A 0x05 +/* SVR Definition (not include major and minor rev) */ +#define SVR_LX2160A 0x873601 +#define SVR_LX2120A 0x873621 +#define SVR_LX2080A 0x873603 /* Number of cores in platform */ /* Used by common code for array initialization */ diff --git a/plat/nxp/soc-lx2160a/soc.c b/plat/nxp/soc-lx2160a/soc.c index 5c77540a71..2209fdad84 100644 --- a/plat/nxp/soc-lx2160a/soc.c +++ b/plat/nxp/soc-lx2160a/soc.c @@ -82,28 +82,6 @@ static const ccn_desc_t plat_ccn_desc = { .master_to_rn_id_map = master_to_rn_id_map }; -/******************************************************************************* - * This function returns the number of clusters in the SoC - ******************************************************************************/ -static unsigned int get_num_cluster(void) -{ - const soc_info_t *soc_info = get_soc_info(); - uint32_t num_clusters = NUMBER_OF_CLUSTERS; - unsigned int i; - - for (i = 0U; i < ARRAY_SIZE(soc_list); i++) { - if (soc_list[i].personality == soc_info->personality) { - num_clusters = soc_list[i].num_clusters; - break; - } - } - - VERBOSE("NUM of cluster = 0x%x\n", num_clusters); - - return num_clusters; -} - - /****************************************************************************** * Function returns the base counter frequency * after reading the first entry at CNTFID0 (0x20 offset). @@ -142,8 +120,10 @@ static gpio_init_info_t gpio_init_data = { static void soc_interconnect_config(void) { unsigned long long val = 0x0U; + uint8_t num_clusters, cores_per_cluster; - uint32_t num_clusters = get_num_cluster(); + get_cluster_info(soc_list, ARRAY_SIZE(soc_list), + &num_clusters, &cores_per_cluster); if (num_clusters == 6U) { ccn_init(&plat_six_cluster_ccn_desc); @@ -464,7 +444,12 @@ void soc_platform_setup(void) ******************************************************************************/ void soc_init(void) { - /* low-level init of the soc */ + uint8_t num_clusters, cores_per_cluster; + + get_cluster_info(soc_list, ARRAY_SIZE(soc_list), + &num_clusters, &cores_per_cluster); + + /* low-level init of the soc */ soc_init_start(); soc_init_percpu(); _init_global_data(); @@ -476,8 +461,6 @@ void soc_init(void) panic(); } - uint32_t num_clusters = get_num_cluster(); - if (num_clusters == 6U) { ccn_init(&plat_six_cluster_ccn_desc); } else { |