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authorAndre Przywara <andre.przywara@arm.com>2020-03-21 11:22:13 +0000
committerAndre Przywara <andre.przywara@arm.com>2020-04-01 15:56:26 +0100
commitaf2a4877a76498a03edb12908164978a7ab0c7fe (patch)
tree59e4543a33ef3974e8d341ee96604a0023807377 /plat
parent07aa0c7e0e13db4b22de135247b4aa3a5b18f15b (diff)
downloadtrusted-firmware-a-af2a4877a76498a03edb12908164978a7ab0c7fe.tar.gz
rpi: rpi3_pwr_domain_on(): Use MMIO accessor
When writing to arbitrary locations in memory using a constructed pointer, there is no guarantee that the compiler does not optimise away the access, since it cannot detect any dependency. One typical solution is to use the "volatile" keyword, but using MMIO accessors in usually the better answer, to avoid torn writes. Replace the usage of an array with such an MMIO accessor function in rpi3_pwr_domain_on(), to make sure the write is really happening. Change-Id: Ia18163c95e92f1557471089fd18abc6dc7fee0c7 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'plat')
-rw-r--r--plat/rpi/common/rpi3_pm.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/plat/rpi/common/rpi3_pm.c b/plat/rpi/common/rpi3_pm.c
index 2a6bf076b0..83270260f6 100644
--- a/plat/rpi/common/rpi3_pm.c
+++ b/plat/rpi/common/rpi3_pm.c
@@ -140,11 +140,14 @@ static int rpi3_pwr_domain_on(u_register_t mpidr)
{
int rc = PSCI_E_SUCCESS;
unsigned int pos = plat_core_pos_by_mpidr(mpidr);
- uint64_t *hold_base = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE;
+ uintptr_t hold_base = PLAT_RPI3_TM_HOLD_BASE;
assert(pos < PLATFORM_CORE_COUNT);
- hold_base[pos] = PLAT_RPI3_TM_HOLD_STATE_GO;
+ hold_base += pos * PLAT_RPI3_TM_HOLD_ENTRY_SIZE;
+
+ mmio_write_64(hold_base, PLAT_RPI3_TM_HOLD_STATE_GO);
+ /* No cache maintenance here, hold_base is mapped as device memory. */
/* Make sure that the write has completed */
dsb();