aboutsummaryrefslogtreecommitdiff
path: root/plat/socionext
diff options
context:
space:
mode:
authorMasahiro Yamada <yamada.masahiro@socionext.com>2020-02-03 19:33:35 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2020-02-12 13:36:58 +0900
commit2d431df8b5ef2e6f751c95dd3f4d8610d29d3379 (patch)
treeb8667e9caccf7d3567446f0bc77ff2097ed45056 /plat/socionext
parentbda9cd70a702b652de318b369ef7b55202fbf49b (diff)
downloadtrusted-firmware-a-2d431df8b5ef2e6f751c95dd3f4d8610d29d3379.tar.gz
uniphier: make pinmon base address configurable
The register base will be changed in the next SoC. Make it configurable. Change-Id: I9fbb6bdd1cf06207618742d4ad7970d911c9bc26 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'plat/socionext')
-rw-r--r--plat/socionext/uniphier/uniphier_boot_device.c26
1 files changed, 21 insertions, 5 deletions
diff --git a/plat/socionext/uniphier/uniphier_boot_device.c b/plat/socionext/uniphier/uniphier_boot_device.c
index 517ec96a48..36a9908be9 100644
--- a/plat/socionext/uniphier/uniphier_boot_device.c
+++ b/plat/socionext/uniphier/uniphier_boot_device.c
@@ -13,8 +13,14 @@
#include "uniphier.h"
-#define UNIPHIER_PINMON0 0x5f900100
-#define UNIPHIER_PINMON2 0x5f900108
+#define UNIPHIER_PINMON0 0x0
+#define UNIPHIER_PINMON2 0x8
+
+static const uintptr_t uniphier_pinmon_base[] = {
+ [UNIPHIER_SOC_LD11] = 0x5f900100,
+ [UNIPHIER_SOC_LD20] = 0x5f900100,
+ [UNIPHIER_SOC_PXS3] = 0x5f900100,
+};
static bool uniphier_ld11_is_usb_boot(uint32_t pinmon)
{
@@ -28,7 +34,8 @@ static bool uniphier_ld20_is_usb_boot(uint32_t pinmon)
static bool uniphier_pxs3_is_usb_boot(uint32_t pinmon)
{
- uint32_t pinmon2 = mmio_read_32(UNIPHIER_PINMON2);
+ uintptr_t pinmon_base = uniphier_pinmon_base[UNIPHIER_SOC_PXS3];
+ uint32_t pinmon2 = mmio_read_32(pinmon_base + UNIPHIER_PINMON2);
return !!(pinmon2 & BIT(31));
}
@@ -133,12 +140,16 @@ static const struct uniphier_boot_device_info uniphier_boot_device_info[] = {
unsigned int uniphier_get_boot_device(unsigned int soc)
{
const struct uniphier_boot_device_info *info;
+ uintptr_t pinmon_base;
uint32_t pinmon;
assert(soc < ARRAY_SIZE(uniphier_boot_device_info));
info = &uniphier_boot_device_info[soc];
- pinmon = mmio_read_32(UNIPHIER_PINMON0);
+ assert(soc < ARRAY_SIZE(uniphier_boot_device_info));
+ pinmon_base = uniphier_pinmon_base[soc];
+
+ pinmon = mmio_read_32(pinmon_base + UNIPHIER_PINMON0);
if (info->have_boot_swap && !(pinmon & BIT(29)))
return UNIPHIER_BOOT_DEVICE_NOR;
@@ -163,7 +174,12 @@ unsigned int uniphier_get_boot_master(unsigned int soc)
assert(soc < ARRAY_SIZE(uniphier_have_onchip_scp));
if (uniphier_have_onchip_scp[soc]) {
- if (mmio_read_32(UNIPHIER_PINMON0) & BIT(27))
+ uintptr_t pinmon_base;
+
+ assert(soc < ARRAY_SIZE(uniphier_boot_device_info));
+ pinmon_base = uniphier_pinmon_base[soc];
+
+ if (mmio_read_32(pinmon_base + UNIPHIER_PINMON0) & BIT(27))
return UNIPHIER_BOOT_MASTER_THIS;
else
return UNIPHIER_BOOT_MASTER_SCP;