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authorHeiko Stuebner <heiko.stuebner@theobroma-systems.com>2019-12-12 11:55:26 +0100
committerHeiko Stuebner <heiko.stuebner@theobroma-systems.com>2019-12-17 10:18:50 +0100
commitdf5a96831764c62deaf30b537987ab349abda2f6 (patch)
treec1c2d4c2d7483ee13a7de30ea45f366f027d0601 /plat/rockchip
parentf55ef85ebfd61d708f6c77465edf3f8d059ca93d (diff)
downloadtrusted-firmware-a-df5a96831764c62deaf30b537987ab349abda2f6.tar.gz
rockchip: make miniloader ddr_parameter handling optional
Transfering the regions of ddr memory to additionally protect is very much specific to some rockchip internal first stage bootloader and doesn't get used in either mainline uboot or even Rockchip's published vendor uboot sources. This results in a big error ERROR: over or zero region, nr=0, max=10 getting emitted on every boot for most users and such a message coming from early firmware might actually confuse developers working with the system. As this mechanism seems to be only be used by Rockchip's internal miniloader hide it behind a build conditional, so it doesn't confuse people too much. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Change-Id: I52c02decc60fd431ea78c7486cad5bac82bdbfbe
Diffstat (limited to 'plat/rockchip')
-rw-r--r--plat/rockchip/px30/drivers/secure/secure.c2
-rw-r--r--plat/rockchip/px30/platform.mk5
-rw-r--r--plat/rockchip/rk3328/drivers/soc/soc.c4
-rw-r--r--plat/rockchip/rk3328/platform.mk5
4 files changed, 13 insertions, 3 deletions
diff --git a/plat/rockchip/px30/drivers/secure/secure.c b/plat/rockchip/px30/drivers/secure/secure.c
index bb2b02ab73..144f94537e 100644
--- a/plat/rockchip/px30/drivers/secure/secure.c
+++ b/plat/rockchip/px30/drivers/secure/secure.c
@@ -62,6 +62,7 @@ void secure_timer_init(void)
void sgrf_init(void)
{
+#ifdef PLAT_RK_SECURE_DDR_MINILOADER
uint32_t i;
struct param_ddr_usage usg;
@@ -74,6 +75,7 @@ void sgrf_init(void)
for (i = 0; i < usg.s_nr; i++)
secure_ddr_region(7 - i, usg.s_top[i], usg.s_base[i]);
+#endif
/* secure the trustzone ram */
secure_ddr_region(0, TZRAM_BASE, TZRAM_SIZE);
diff --git a/plat/rockchip/px30/platform.mk b/plat/rockchip/px30/platform.mk
index d1299d4afe..87cf18704a 100644
--- a/plat/rockchip/px30/platform.mk
+++ b/plat/rockchip/px30/platform.mk
@@ -46,7 +46,6 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \
${RK_PLAT_COMMON}/aarch64/plat_helpers.S \
${RK_PLAT_COMMON}/aarch64/platform_common.c \
${RK_PLAT_COMMON}/bl31_plat_setup.c \
- ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c \
${RK_PLAT_COMMON}/params_setup.c \
${RK_PLAT_COMMON}/pmusram/cpus_on_fixed_addr.S \
${RK_PLAT_COMMON}/plat_pm.c \
@@ -57,6 +56,10 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \
${RK_PLAT_SOC}/drivers/soc/soc.c \
${RK_PLAT_SOC}/plat_sip_calls.c
+ifdef PLAT_RK_SECURE_DDR_MINILOADER
+BL31_SOURCES += ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c
+endif
+
ENABLE_PLAT_COMPAT := 0
MULTI_CONSOLE_API := 1
diff --git a/plat/rockchip/rk3328/drivers/soc/soc.c b/plat/rockchip/rk3328/drivers/soc/soc.c
index 59d857244a..306308f3f1 100644
--- a/plat/rockchip/rk3328/drivers/soc/soc.c
+++ b/plat/rockchip/rk3328/drivers/soc/soc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -97,6 +97,7 @@ void secure_timer_init(void)
void sgrf_init(void)
{
+#ifdef PLAT_RK_SECURE_DDR_MINILOADER
uint32_t i, val;
struct param_ddr_usage usg;
@@ -115,6 +116,7 @@ void sgrf_init(void)
FIREWALL_DDR_FW_DDR_RGN(7 - i),
RG_MAP_SECURE(usg.s_top[i], usg.s_base[i]));
}
+#endif
/* set ddr rgn0_top and rga0_top as 0 */
mmio_write_32(FIREWALL_DDR_BASE + FIREWALL_DDR_FW_DDR_RGN(0), 0x0);
diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk
index 0da4f2dc46..0c5cfae9b6 100644
--- a/plat/rockchip/rk3328/platform.mk
+++ b/plat/rockchip/rk3328/platform.mk
@@ -42,7 +42,6 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \
drivers/delay_timer/generic_delay_timer.c \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
- ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c \
${RK_PLAT_COMMON}/aarch64/plat_helpers.S \
${RK_PLAT_COMMON}/params_setup.c \
${RK_PLAT_COMMON}/bl31_plat_setup.c \
@@ -53,6 +52,10 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \
${RK_PLAT_SOC}/drivers/pmu/pmu.c \
${RK_PLAT_SOC}/drivers/soc/soc.c
+ifdef PLAT_RK_SECURE_DDR_MINILOADER
+BL31_SOURCES += ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c
+endif
+
include lib/coreboot/coreboot.mk
include lib/libfdt/libfdt.mk