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authorPaul Beesley <paul.beesley@arm.com>2019-08-15 15:30:13 +0000
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2019-08-15 15:30:13 +0000
commit99becbe3dff999c4a54bf641b5afe846d3ac20a8 (patch)
treed238ef22f27151aa7f85cc7c2daaa8731fa984be /plat/rockchip
parent585df3b49b8eb038bab2d48f2b320465a09da197 (diff)
parent0eb7fa91e18bd888d94cd8d92f033ba92d9cb818 (diff)
downloadtrusted-firmware-a-99becbe3dff999c4a54bf641b5afe846d3ac20a8.tar.gz
Merge changes from topic "rockchip-uart-fixes" into integration
* changes: rockchip: rk3399: store actual debug uart information on suspend rockchip: move dt-coreboot uart distinction into param handling code rockchip: make uart baudrate configurable rockchip: px30: add uart5 as option for serial output
Diffstat (limited to 'plat/rockchip')
-rw-r--r--plat/rockchip/common/bl31_plat_setup.c15
-rw-r--r--plat/rockchip/common/include/plat_private.h2
-rw-r--r--plat/rockchip/common/params_setup.c68
-rw-r--r--plat/rockchip/common/sp_min_plat_setup.c16
-rw-r--r--plat/rockchip/px30/px30_def.h3
-rw-r--r--plat/rockchip/rk3399/drivers/pmu/pmu.c43
6 files changed, 101 insertions, 46 deletions
diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c
index a13ee495a2..c4a03592ea 100644
--- a/plat/rockchip/common/bl31_plat_setup.c
+++ b/plat/rockchip/common/bl31_plat_setup.c
@@ -14,7 +14,6 @@
#include <drivers/console.h>
#include <drivers/generic_delay_timer.h>
#include <drivers/ti/uart/uart_16550.h>
-#include <lib/coreboot.h>
#include <lib/mmio.h>
#include <plat_private.h>
#include <plat/common/platform.h>
@@ -62,16 +61,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
params_early_setup(arg1);
-#if COREBOOT
- if (coreboot_serial.type)
- console_16550_register(coreboot_serial.baseaddr,
- coreboot_serial.input_hertz,
- coreboot_serial.baud,
- &console);
-#else
- console_16550_register(rockchip_get_uart_base(), PLAT_RK_UART_CLOCK,
- PLAT_RK_UART_BAUDRATE, &console);
-#endif
+ if (rockchip_get_uart_base() != 0)
+ console_16550_register(rockchip_get_uart_base(),
+ rockchip_get_uart_clock(),
+ rockchip_get_uart_baudrate(), &console);
VERBOSE("bl31_setup\n");
diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h
index 714a8bf9e6..990d1065fd 100644
--- a/plat/rockchip/common/include/plat_private.h
+++ b/plat/rockchip/common/include/plat_private.h
@@ -139,6 +139,8 @@ extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT];
extern const mmap_region_t plat_rk_mmap[];
uint32_t rockchip_get_uart_base(void);
+uint32_t rockchip_get_uart_baudrate(void);
+uint32_t rockchip_get_uart_clock(void);
#endif /* __ASSEMBLER__ */
diff --git a/plat/rockchip/common/params_setup.c b/plat/rockchip/common/params_setup.c
index d0fea4ffa6..8c2e5e911b 100644
--- a/plat/rockchip/common/params_setup.c
+++ b/plat/rockchip/common/params_setup.c
@@ -26,12 +26,6 @@ static struct bl_aux_gpio_info poweroff_gpio;
static struct bl_aux_gpio_info suspend_gpio[10];
uint32_t suspend_gpio_cnt;
static struct bl_aux_rk_apio_info suspend_apio;
-static uint32_t rk_uart_base = PLAT_RK_UART_BASE;
-
-uint32_t rockchip_get_uart_base(void)
-{
- return rk_uart_base;
-}
#if COREBOOT
static int dt_process_fdt(u_register_t param_from_bl2)
@@ -39,6 +33,9 @@ static int dt_process_fdt(u_register_t param_from_bl2)
return -ENODEV;
}
#else
+static uint32_t rk_uart_base = PLAT_RK_UART_BASE;
+static uint32_t rk_uart_baudrate = PLAT_RK_UART_BAUDRATE;
+static uint32_t rk_uart_clock = PLAT_RK_UART_CLOCK;
static uint8_t fdt_buffer[0x10000];
void *plat_get_fdt(void)
@@ -53,9 +50,12 @@ static void plat_rockchip_dt_process_fdt_uart(void *fdt)
int node_offset;
int stdout_path_len;
const char *stdout_path;
+ const char *separator;
+ const char *baud_start;
char serial_char;
int serial_no;
uint32_t uart_base;
+ uint32_t baud;
node_offset = fdt_path_offset(fdt, path_name);
if (node_offset < 0)
@@ -68,7 +68,7 @@ static void plat_rockchip_dt_process_fdt_uart(void *fdt)
/*
* We expect something like:
- * "serial0:...""
+ * "serial0:baudrate"
*/
if (strncmp("serial", stdout_path, 6) != 0)
return;
@@ -96,11 +96,38 @@ static void plat_rockchip_dt_process_fdt_uart(void *fdt)
uart_base = UART4_BASE;
break;
#endif
+#ifdef UART5_BASE
+ case 5:
+ uart_base = UART5_BASE;
+ break;
+#endif
default:
return;
}
rk_uart_base = uart_base;
+
+ separator = strchr(stdout_path, ':');
+ if (!separator)
+ return;
+
+ baud = 0;
+ baud_start = separator + 1;
+ while (*baud_start != '\0') {
+ /*
+ * uart binding is <baud>{<parity>{<bits>{...}}}
+ * So the baudrate either is the whole string, or
+ * we end in the parity characters.
+ */
+ if (*baud_start == 'n' || *baud_start == 'o' ||
+ *baud_start == 'e')
+ break;
+
+ baud = baud * 10 + (*baud_start - '0');
+ baud_start++;
+ }
+
+ rk_uart_baudrate = baud;
}
static int dt_process_fdt(u_register_t param_from_bl2)
@@ -118,6 +145,33 @@ static int dt_process_fdt(u_register_t param_from_bl2)
}
#endif
+uint32_t rockchip_get_uart_base(void)
+{
+#if COREBOOT
+ return coreboot_serial.baseaddr;
+#else
+ return rk_uart_base;
+#endif
+}
+
+uint32_t rockchip_get_uart_baudrate(void)
+{
+#if COREBOOT
+ return coreboot_serial.baud;
+#else
+ return rk_uart_baudrate;
+#endif
+}
+
+uint32_t rockchip_get_uart_clock(void)
+{
+#if COREBOOT
+ return coreboot_serial.input_hertz;
+#else
+ return rk_uart_clock;
+#endif
+}
+
struct bl_aux_gpio_info *plat_get_rockchip_gpio_reset(void)
{
return &rst_gpio;
diff --git a/plat/rockchip/common/sp_min_plat_setup.c b/plat/rockchip/common/sp_min_plat_setup.c
index 7b1a0b58b7..6d15075f2a 100644
--- a/plat/rockchip/common/sp_min_plat_setup.c
+++ b/plat/rockchip/common/sp_min_plat_setup.c
@@ -15,7 +15,6 @@
#include <drivers/console.h>
#include <drivers/generic_delay_timer.h>
#include <drivers/ti/uart/uart_16550.h>
-#include <lib/coreboot.h>
#include <lib/mmio.h>
#include <plat_private.h>
#include <plat/common/platform.h>
@@ -57,16 +56,11 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
params_early_setup(arg1);
-#if COREBOOT
- if (coreboot_serial.type)
- console_16550_register(coreboot_serial.baseaddr,
- coreboot_serial.input_hertz,
- coreboot_serial.baud,
- &console);
-#else
- console_16550_register(rockchip_get_uart_base(), PLAT_RK_UART_CLOCK,
- PLAT_RK_UART_BAUDRATE, &console);
-#endif
+ if (rockchip_get_uart_base() != 0)
+ console_16550_register(rockchip_get_uart_base(),
+ rockchip_get_uart_clock(),
+ rockchip_get_uart_baudrate(), &console);
+
VERBOSE("sp_min_setup\n");
bl31_params_parse_helper(arg0, NULL, &bl33_ep_info);
diff --git a/plat/rockchip/px30/px30_def.h b/plat/rockchip/px30/px30_def.h
index 021165a4a3..9b8ccfca63 100644
--- a/plat/rockchip/px30/px30_def.h
+++ b/plat/rockchip/px30/px30_def.h
@@ -54,6 +54,9 @@
#define UART2_BASE 0xff160000
#define UART2_SIZE SIZE_K(64)
+#define UART5_BASE 0xff178000
+#define UART5_SIZE SIZE_K(64)
+
#define I2C0_BASE 0xff180000
#define I2C0_SIZE SIZE_K(64)
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index a6b5973601..30941fd077 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -1125,32 +1125,41 @@ static struct uart_debug uart_save;
void suspend_uart(void)
{
- uart_save.uart_lcr = mmio_read_32(PLAT_RK_UART_BASE + UART_LCR);
- uart_save.uart_ier = mmio_read_32(PLAT_RK_UART_BASE + UART_IER);
- uart_save.uart_mcr = mmio_read_32(PLAT_RK_UART_BASE + UART_MCR);
- mmio_write_32(PLAT_RK_UART_BASE + UART_LCR,
+ uint32_t uart_base = rockchip_get_uart_base();
+
+ if (uart_base == 0)
+ return;
+
+ uart_save.uart_lcr = mmio_read_32(uart_base + UART_LCR);
+ uart_save.uart_ier = mmio_read_32(uart_base + UART_IER);
+ uart_save.uart_mcr = mmio_read_32(uart_base + UART_MCR);
+ mmio_write_32(uart_base + UART_LCR,
uart_save.uart_lcr | UARTLCR_DLAB);
- uart_save.uart_dll = mmio_read_32(PLAT_RK_UART_BASE + UART_DLL);
- uart_save.uart_dlh = mmio_read_32(PLAT_RK_UART_BASE + UART_DLH);
- mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_save.uart_lcr);
+ uart_save.uart_dll = mmio_read_32(uart_base + UART_DLL);
+ uart_save.uart_dlh = mmio_read_32(uart_base + UART_DLH);
+ mmio_write_32(uart_base + UART_LCR, uart_save.uart_lcr);
}
void resume_uart(void)
{
+ uint32_t uart_base = rockchip_get_uart_base();
uint32_t uart_lcr;
- mmio_write_32(PLAT_RK_UART_BASE + UARTSRR,
+ if (uart_base == 0)
+ return;
+
+ mmio_write_32(uart_base + UARTSRR,
XMIT_FIFO_RESET | RCVR_FIFO_RESET | UART_RESET);
- uart_lcr = mmio_read_32(PLAT_RK_UART_BASE + UART_LCR);
- mmio_write_32(PLAT_RK_UART_BASE + UART_MCR, DIAGNOSTIC_MODE);
- mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_lcr | UARTLCR_DLAB);
- mmio_write_32(PLAT_RK_UART_BASE + UART_DLL, uart_save.uart_dll);
- mmio_write_32(PLAT_RK_UART_BASE + UART_DLH, uart_save.uart_dlh);
- mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_save.uart_lcr);
- mmio_write_32(PLAT_RK_UART_BASE + UART_IER, uart_save.uart_ier);
- mmio_write_32(PLAT_RK_UART_BASE + UART_FCR, UARTFCR_FIFOEN);
- mmio_write_32(PLAT_RK_UART_BASE + UART_MCR, uart_save.uart_mcr);
+ uart_lcr = mmio_read_32(uart_base + UART_LCR);
+ mmio_write_32(uart_base + UART_MCR, DIAGNOSTIC_MODE);
+ mmio_write_32(uart_base + UART_LCR, uart_lcr | UARTLCR_DLAB);
+ mmio_write_32(uart_base + UART_DLL, uart_save.uart_dll);
+ mmio_write_32(uart_base + UART_DLH, uart_save.uart_dlh);
+ mmio_write_32(uart_base + UART_LCR, uart_save.uart_lcr);
+ mmio_write_32(uart_base + UART_IER, uart_save.uart_ier);
+ mmio_write_32(uart_base + UART_FCR, UARTFCR_FIFOEN);
+ mmio_write_32(uart_base + UART_MCR, uart_save.uart_mcr);
}
void save_usbphy(void)