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authorXing Zheng <zhengxing@rock-chips.com>2017-02-24 14:47:51 +0800
committerXing Zheng <zhengxing@rock-chips.com>2017-02-24 20:07:44 +0800
commit941c71475e1b7a3ac41e61aac1ed5d3b7304b59b (patch)
treee2c4de93f06c9c5905341200adbc9314846d6661 /plat/rockchip/rk3399/include/platform_def.h
parent1830f7901e110a6407d449506a0fc93146af6833 (diff)
downloadtrusted-firmware-a-941c71475e1b7a3ac41e61aac1ed5d3b7304b59b.tar.gz
rockchip: rk3399: configure the DDR secure region for BL31 image
Move the BL31 loaded base address 0x10000 to 0x1000, and configure the the memory range 0~1MB is secure, the goal is that make sure the BL31 image will be not modified. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Diffstat (limited to 'plat/rockchip/rk3399/include/platform_def.h')
-rw-r--r--plat/rockchip/rk3399/include/platform_def.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/plat/rockchip/rk3399/include/platform_def.h b/plat/rockchip/rk3399/include/platform_def.h
index 6fb9d98655..b83b891ee5 100644
--- a/plat/rockchip/rk3399/include/platform_def.h
+++ b/plat/rockchip/rk3399/include/platform_def.h
@@ -91,9 +91,9 @@
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
-/* TF txet, ro, rw, Size: 512KB */
+/* TF text, ro, rw, Size: 1MB */
#define TZRAM_BASE (0x0)
-#define TZRAM_SIZE (0x80000)
+#define TZRAM_SIZE (0x100000)
/*******************************************************************************
* BL31 specific defines.
@@ -101,7 +101,7 @@
/*
* Put BL3-1 at the top of the Trusted RAM
*/
-#define BL31_BASE (TZRAM_BASE + 0x10000)
+#define BL31_BASE (TZRAM_BASE + 0x1000)
#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/*******************************************************************************