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authorDerek Basehore <dbasehore@chromium.org>2018-01-23 16:24:43 -0800
committerDerek Basehore <dbasehore@chromium.org>2018-01-23 17:42:54 -0800
commit8c1e78af46d80c3e56b83647dd40d1207577c667 (patch)
tree77e8ca59c0a8478887fdfc18295f2b42799049c2 /plat/rockchip/rk3399/drivers
parentb2a0af1bff73c70eec09efa047e9ca20ce455077 (diff)
downloadtrusted-firmware-a-8c1e78af46d80c3e56b83647dd40d1207577c667.tar.gz
rockchip/rk3399: Add udelay to wait loops
We were looping for MAX_WAIT_COUNT in several places without any delays, so this adds the delays to make those loops more predictable. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Diffstat (limited to 'plat/rockchip/rk3399/drivers')
-rw-r--r--plat/rockchip/rk3399/drivers/pmu/pmu.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index df8152f4f8..05fa5cadf6 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -79,9 +79,12 @@ static void pmu_bus_idle_req(uint32_t bus, uint32_t state)
do {
bus_state = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & bus_id;
bus_ack = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK) & bus_id;
+ if (bus_state == bus_req && bus_ack == bus_req)
+ break;
+
wait_cnt++;
- } while ((bus_state != bus_req || bus_ack != bus_req) &&
- (wait_cnt < MAX_WAIT_COUNT));
+ udelay(1);
+ } while (wait_cnt < MAX_WAIT_COUNT);
if (bus_state != bus_req || bus_ack != bus_req) {
INFO("%s:st=%x(%x)\n", __func__,
@@ -430,6 +433,7 @@ static void pmu_scu_b_pwrdn(void)
while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) &
BIT(STANDBY_BY_WFIL2_CLUSTER_B))) {
wait_cnt++;
+ udelay(1);
if (wait_cnt >= MAX_WAIT_COUNT)
ERROR("%s:wait cluster-b l2(%x)\n", __func__,
mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST));
@@ -1369,6 +1373,7 @@ int rockchip_soc_sys_pwr_dm_suspend(void)
mmio_read_32(PMU_BASE + PMU_ADB400_ST));
panic();
}
+ udelay(1);
}
mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN));
@@ -1462,6 +1467,7 @@ int rockchip_soc_sys_pwr_dm_resume(void)
mmio_read_32(PMU_BASE + PMU_ADB400_ST));
panic();
}
+ udelay(1);
}
pmu_sgrf_rst_hld_release();