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authorJonathan Wright <jonathan.wright@arm.com>2018-03-14 15:24:00 +0000
committerJonathan Wright <jonathan.wright@arm.com>2018-03-26 12:43:05 +0100
commit649c48f5dca1765eabd42b5d630736a5d1e1f5e2 (patch)
tree48e9700b7154e62d0e8b43e732346e3929b938a3 /plat/rockchip/rk3399/drivers
parent3eacacc0ef6a8beefd858ff36cbc35e2b9ff5b07 (diff)
downloadtrusted-firmware-a-649c48f5dca1765eabd42b5d630736a5d1e1f5e2.tar.gz
plat: fix switch statements to comply with MISRA rules
Ensure (where possible) that switch statements in plat comply with MISRA rules 16.1 - 16.7. Change-Id: Ie4a7d2fd10f6141c0cfb89317ea28a755391622f Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
Diffstat (limited to 'plat/rockchip/rk3399/drivers')
-rw-r--r--plat/rockchip/rk3399/drivers/dram/dfs.c3
-rw-r--r--plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c3
-rw-r--r--plat/rockchip/rk3399/drivers/pmu/pmu.c24
3 files changed, 11 insertions, 19 deletions
diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c
index d629e4bfb6..70d9423b31 100644
--- a/plat/rockchip/rk3399/drivers/dram/dfs.c
+++ b/plat/rockchip/rk3399/drivers/dram/dfs.c
@@ -207,6 +207,9 @@ static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config,
ptiming_config->rdbi = 0;
ptiming_config->wdbi = 0;
break;
+ default:
+ /* Do nothing in default case */
+ break;
}
ptiming_config->dramds = drv_config->dram_side_drv;
ptiming_config->dramodt = drv_config->dram_side_dq_odt;
diff --git a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c
index 2e196b54c1..3527f0e5ec 100644
--- a/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c
+++ b/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c
@@ -1314,5 +1314,8 @@ void dram_get_parameter(struct timing_related_config *timing_config,
case LPDDR4:
lpddr4_get_parameter(timing_config, pdram_timing);
break;
+ default:
+ /* Do nothing in default case */
+ break;
}
}
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index caea7a7237..ed1ea8b63c 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -310,6 +310,7 @@ static int pmu_set_power_domain(uint32_t pd_id, uint32_t pd_state)
pmu_bus_idle_req(BUS_ID_PERIHP, state);
break;
default:
+ /* Do nothing in default case */
break;
}
@@ -647,12 +648,8 @@ int rockchip_soc_cores_pwr_dm_off(void)
int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,
plat_local_state_t lvl_state)
{
- switch (lvl) {
- case MPIDR_AFFLVL1:
+ if (lvl == MPIDR_AFFLVL1) {
clst_pwr_domain_suspend(lvl_state);
- break;
- default:
- break;
}
return PSCI_E_SUCCESS;
@@ -675,12 +672,8 @@ int rockchip_soc_cores_pwr_dm_suspend(void)
int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, plat_local_state_t lvl_state)
{
- switch (lvl) {
- case MPIDR_AFFLVL1:
+ if (lvl == MPIDR_AFFLVL1) {
clst_pwr_domain_suspend(lvl_state);
- break;
- default:
- break;
}
return PSCI_E_SUCCESS;
@@ -698,12 +691,8 @@ int rockchip_soc_cores_pwr_dm_on_finish(void)
int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl,
plat_local_state_t lvl_state)
{
- switch (lvl) {
- case MPIDR_AFFLVL1:
+ if (lvl == MPIDR_AFFLVL1) {
clst_pwr_domain_resume(lvl_state);
- break;
- default:
- break;
}
return PSCI_E_SUCCESS;
@@ -721,11 +710,8 @@ int rockchip_soc_cores_pwr_dm_resume(void)
int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, plat_local_state_t lvl_state)
{
- switch (lvl) {
- case MPIDR_AFFLVL1:
+ if (lvl == MPIDR_AFFLVL1) {
clst_pwr_domain_resume(lvl_state);
- default:
- break;
}
return PSCI_E_SUCCESS;