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authorLin Huang <hl@rock-chips.com>2018-03-20 09:37:21 +0800
committerCaesar Wang <wxt@rock-chips.com>2018-03-20 09:42:27 +0800
commit56bf9407308fe5eb611f6414d85cca4aef125ed9 (patch)
treed5251b30d8a618a44327a48d8174a79ef376d2e0 /plat/rockchip/rk3399/drivers
parentfb45044bc567b96e8be243b717ec2920224cd9b9 (diff)
downloadtrusted-firmware-a-56bf9407308fe5eb611f6414d85cca4aef125ed9.tar.gz
rockchip/rk3399: save/restore watchdog register correctly
there are two fix for save/restore watchdog register: 1. watchdog plck will shutdown after secure_watchdog_disable(), so need to save register before it and restore after secure_watchdog_enable(). 2. need write 0x76 to cnt_restart to keep watchdog alive when restore watchdog register. Change-Id: I1f6fbceae22186e3b72a87df6332a110adf37479 Signed-off-by: Lin Huang <hl@rock-chips.com>
Diffstat (limited to 'plat/rockchip/rk3399/drivers')
-rw-r--r--plat/rockchip/rk3399/drivers/pmu/pmu.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index f4893efe8d..caea7a7237 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -1319,10 +1319,14 @@ void wdt_register_restore(void)
{
int i;
- for (i = 0; i < 2; i++) {
+ for (i = 1; i >= 0; i--) {
mmio_write_32(WDT0_BASE + i * 4, store_wdt0[i]);
mmio_write_32(WDT1_BASE + i * 4, store_wdt1[i]);
}
+
+ /* write 0x76 to cnt_restart to keep watchdog alive */
+ mmio_write_32(WDT0_BASE + 0x0c, 0x76);
+ mmio_write_32(WDT1_BASE + 0x0c, 0x76);
}
int rockchip_soc_sys_pwr_dm_suspend(void)
@@ -1383,6 +1387,7 @@ int rockchip_soc_sys_pwr_dm_suspend(void)
}
mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN));
+ wdt_register_save();
secure_watchdog_disable();
/*
@@ -1398,7 +1403,6 @@ int rockchip_soc_sys_pwr_dm_suspend(void)
suspend_uart();
grf_register_save();
cru_register_save();
- wdt_register_save();
sram_save();
plat_rockchip_save_gpio();
@@ -1411,7 +1415,6 @@ int rockchip_soc_sys_pwr_dm_resume(void)
uint32_t status = 0;
plat_rockchip_restore_gpio();
- wdt_register_restore();
cru_register_restore();
grf_register_restore();
resume_uart();
@@ -1426,6 +1429,7 @@ int rockchip_soc_sys_pwr_dm_resume(void)
secure_watchdog_enable();
secure_sgrf_init();
secure_sgrf_ddr_rgn_init();
+ wdt_register_restore();
/* restore clk_ddrc_bpll_src_en gate */
mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3),