diff options
author | Lin Huang <hl@rock-chips.com> | 2017-05-04 16:02:45 +0800 |
---|---|---|
committer | Caesar Wang <wxt@rock-chips.com> | 2017-06-08 09:59:49 +0800 |
commit | bc5c30073e1ec28407e22727848df1adda433636 (patch) | |
tree | 70ecde7908a2fa53a36573e7219a2cc4338add97 /plat/rockchip/rk3328 | |
parent | a9059b9643932782c17a9a5366f7019817819d44 (diff) | |
download | trusted-firmware-a-bc5c30073e1ec28407e22727848df1adda433636.tar.gz |
rockchip: add pmusram section
the function pmu_cpuon_entrypoint() need to run in the pmusram,
we just copy bin file to pmusram before, now we add pmusram section
and link pmu_cpuon_entrypoint() to pmusram directly
Change-Id: Iae31e4c01c480c8e6f565a8f588332b478efdb16
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Diffstat (limited to 'plat/rockchip/rk3328')
-rw-r--r-- | plat/rockchip/rk3328/drivers/pmu/pmu.c | 70 | ||||
-rw-r--r-- | plat/rockchip/rk3328/include/plat.ld.S | 44 | ||||
-rw-r--r-- | plat/rockchip/rk3328/include/platform_def.h | 2 | ||||
-rw-r--r-- | plat/rockchip/rk3328/platform.mk | 1 |
4 files changed, 38 insertions, 79 deletions
diff --git a/plat/rockchip/rk3328/drivers/pmu/pmu.c b/plat/rockchip/rk3328/drivers/pmu/pmu.c index 59d399be4b..60f36d31b8 100644 --- a/plat/rockchip/rk3328/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3328/drivers/pmu/pmu.c @@ -16,16 +16,12 @@ #include <platform.h> #include <platform_def.h> #include <plat_private.h> -#include <pmu_sram.h> #include <pmu.h> #include <rk3328_def.h> #include <pmu_com.h> DEFINE_BAKERY_LOCK(rockchip_pd_lock); -static struct psram_data_t *psram_sleep_cfg = - (struct psram_data_t *)PSRAM_DT_BASE; - static struct rk3328_sleep_ddr_data ddr_data; static __sramdata struct rk3328_sleep_sram_data sram_data; @@ -34,22 +30,6 @@ static uint32_t cpu_warm_boot_addr; #pragma weak rk3328_pmic_suspend #pragma weak rk3328_pmic_resume -void plat_rockchip_pmusram_prepare(void) -{ - uint32_t *sram_dst, *sram_src; - size_t sram_size = 2; - /* - * pmu sram code and data prepare - */ - sram_dst = (uint32_t *)PMUSRAM_BASE; - sram_src = (uint32_t *)&pmu_cpuson_entrypoint_start; - sram_size = (uint32_t *)&pmu_cpuson_entrypoint_end - - (uint32_t *)sram_src; - u32_align_cpy(sram_dst, sram_src, sram_size); - - psram_sleep_cfg->sp = PSRAM_DT_BASE; -} - static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id) { uint32_t pd_reg, apm_reg; @@ -140,6 +120,16 @@ static void nonboot_cpus_off(void) } } +void sram_save(void) +{ + /* TODO: support the sdram save for rk3328 SoCs*/ +} + +void sram_restore(void) +{ + /* TODO: support the sdram restore for rk3328 SoCs */ +} + int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint) { uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); @@ -495,11 +485,6 @@ __sramfunc void rk3328_pmic_resume(void) sram_udelay(100); } -static inline void rockchip_set_sram_sp(uint64_t set_sp) -{ - __asm volatile("mov sp, %0\n"::"r" (set_sp) : "sp"); -} - static __sramfunc void ddr_suspend(void) { sram_data.pd_sr_idle_save = mmio_read_32(DDR_UPCTL_BASE + @@ -538,7 +523,7 @@ static __sramfunc void ddr_suspend(void) dpll_suspend(); } -static __sramfunc void ddr_resume(void) +__sramfunc void dmc_restore(void) { dpll_resume(); @@ -574,7 +559,7 @@ static __sramfunc void sram_dbg_uart_suspend(void) mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(2), 0x00040004); } -static __sramfunc void sram_dbg_uart_resume(void) +__sramfunc void sram_dbg_uart_resume(void) { /* restore uart clk and reset fifo */ mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(16), 0x20000000); @@ -610,7 +595,7 @@ __sramfunc void sram_suspend(void) disable_mmu_icache_el3(); mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), - (PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) | + ((uintptr_t)&pmu_cpuson_entrypoint >> CPU_BOOT_ADDR_ALIGN) | CPU_BOOT_ADDR_WMASK); /* ddr self-refresh and gating phy */ @@ -623,28 +608,8 @@ __sramfunc void sram_suspend(void) sram_soc_enter_lp(); } -static __sramfunc void sys_resume_first(void) -{ - sram_dbg_uart_resume(); - - rk3328_pmic_resume(); - - /* ddr self-refresh exit */ - ddr_resume(); - - /* disable apm cfg */ - mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(0), CORES_PM_DISABLE); - - /* the warm booting address of cpus */ - mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), - (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) | - CPU_BOOT_ADDR_WMASK); -} - void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void) { - rockchip_set_sram_sp(PSRAM_DT_BASE); - sram_suspend(); /* should never reach here */ @@ -671,6 +636,11 @@ int rockchip_soc_sys_pwr_dm_resume(void) return 0; } +void rockchip_plat_mmu_el3(void) +{ + /* TODO: support the el3 for rk3328 SoCs */ +} + void plat_rockchip_pmu_init(void) { uint32_t cpu; @@ -679,10 +649,6 @@ void plat_rockchip_pmu_init(void) cpuson_flags[cpu] = 0; cpu_warm_boot_addr = (uint64_t)platform_cpu_warmboot; - psram_sleep_cfg->ddr_func = (uint64_t)sys_resume_first; - psram_sleep_cfg->ddr_data = 0x00; - psram_sleep_cfg->ddr_flag = 0x01; - psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff; /* the warm booting address of cpus */ mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), diff --git a/plat/rockchip/rk3328/include/plat.ld.S b/plat/rockchip/rk3328/include/plat.ld.S index ff17572d0c..b3559b20f6 100644 --- a/plat/rockchip/rk3328/include/plat.ld.S +++ b/plat/rockchip/rk3328/include/plat.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,39 +7,31 @@ #define __ROCKCHIP_PLAT_LD_S__ MEMORY { - SRAM (rwx): ORIGIN = SRAM_LDS_BASE, LENGTH = SRAM_LDS_SIZE + PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE } SECTIONS { - . = SRAM_LDS_BASE; - ASSERT(. == ALIGN(4096), - "SRAM_BASE address is not aligned on a page boundary.") + . = PMUSRAM_BASE; /* - * The SRAM space allocation for RK3328 - * ---------------- - * | sram text - * ---------------- - * | sram data - * ---------------- + * pmu_cpuson_entrypoint request address + * align 64K when resume, so put it in the + * start of pmusram */ - .text_sram : ALIGN(4096) { - __bl31_sram_text_start = .; - *(.sram.text) - *(.sram.rodata) - . = ALIGN(4096); - __bl31_sram_text_end = .; - } >SRAM + .text_pmusram : { + ASSERT(. == ALIGN(64 * 1024), + ".pmusram.entry request 64K aligned."); + *(.pmusram.entry) + __bl31_pmusram_text_start = .; + *(.pmusram.text) + *(.pmusram.rodata) + __bl31_pmusram_text_end = .; + __bl31_pmusram_data_start = .; + *(.pmusram.data) + __bl31_pmusram_data_end = .; - .data_sram : ALIGN(4096) { - __bl31_sram_data_start = .; - *(.sram.data) - . = ALIGN(4096); - __bl31_sram_data_end = .; - } >SRAM - __sram_incbin_start = .; - __sram_incbin_end = .; + } >PMUSRAM } #endif /* __ROCKCHIP_PLAT_LD_S__ */ diff --git a/plat/rockchip/rk3328/include/platform_def.h b/plat/rockchip/rk3328/include/platform_def.h index 1f49fcdc96..9b192884e3 100644 --- a/plat/rockchip/rk3328/include/platform_def.h +++ b/plat/rockchip/rk3328/include/platform_def.h @@ -120,4 +120,6 @@ #define PLAT_RK_PRIMARY_CPU 0x0 +#define PSRAM_DO_DDR_RESUME 0 + #endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk index b81d746b11..8863fb4ffc 100644 --- a/plat/rockchip/rk3328/platform.mk +++ b/plat/rockchip/rk3328/platform.mk @@ -41,7 +41,6 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \ ${RK_PLAT_COMMON}/drivers/parameter/ddr_parameter.c \ ${RK_PLAT_COMMON}/aarch64/plat_helpers.S \ ${RK_PLAT_COMMON}/bl31_plat_setup.c \ - ${RK_PLAT_COMMON}/pmusram/pmu_sram.c \ ${RK_PLAT_COMMON}/pmusram/pmu_sram_cpus_on.S \ ${RK_PLAT_COMMON}/plat_pm.c \ ${RK_PLAT_COMMON}/plat_topology.c \ |