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author | Justin Chadwell <justin.chadwell@arm.com> | 2019-07-03 14:11:28 +0100 |
---|---|---|
committer | Justin Chadwell <justin.chadwell@arm.com> | 2019-07-11 12:10:58 +0100 |
commit | 79ca7807cc00fb262b3c9e202f19dbbcb618f228 (patch) | |
tree | 10da9b7fc612c75e641fedee95cdb3567e04dc73 /plat/rockchip/rk3328 | |
parent | 673406b50841ca45b3f041283a0d5f750611470e (diff) | |
download | trusted-firmware-a-79ca7807cc00fb262b3c9e202f19dbbcb618f228.tar.gz |
Update rockchip platform to not rely on undefined overflow behaviour
This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.
Change-Id: Ib7fc54e4141cc4f1952a18241bc18671b36e2168
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
Diffstat (limited to 'plat/rockchip/rk3328')
-rw-r--r-- | plat/rockchip/rk3328/drivers/pmu/pmu.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/plat/rockchip/rk3328/drivers/pmu/pmu.c b/plat/rockchip/rk3328/drivers/pmu/pmu.c index c215ee2400..a17fef9e10 100644 --- a/plat/rockchip/rk3328/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3328/drivers/pmu/pmu.c @@ -284,7 +284,7 @@ static inline void pm_pll_wait_lock(uint32_t pll_id) static inline void pll_pwr_dwn(uint32_t pll_id, uint32_t pd) { mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), - BITS_WITH_WMASK(1, 1, 15)); + BITS_WITH_WMASK(1U, 1U, 15)); if (pd) mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), BITS_WITH_WMASK(1, 1, 14)); @@ -305,7 +305,7 @@ static __sramfunc void dpll_suspend(void) sram_data.dpll_con_save[i] = mmio_read_32(CRU_BASE + PLL_CONS(DPLL_ID, i)); mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), - BITS_WITH_WMASK(1, 1, 15)); + BITS_WITH_WMASK(1U, 1U, 15)); mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), BITS_WITH_WMASK(1, 1, 14)); } @@ -315,7 +315,7 @@ static __sramfunc void dpll_resume(void) uint32_t delay = PLL_LOCKED_TIMEOUT; mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), - BITS_WITH_WMASK(1, 1, 15)); + BITS_WITH_WMASK(1U, 1U, 15)); mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), BITS_WITH_WMASK(0, 1, 14)); mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), @@ -402,7 +402,7 @@ static void pm_plls_suspend(void) /* clk_rtc32k */ mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(38), BITS_WITH_WMASK(767, 0x3fff, 0) | - BITS_WITH_WMASK(2, 0x3, 14)); + BITS_WITH_WMASK(2U, 0x3u, 14)); } static void pm_plls_resume(void) @@ -411,7 +411,7 @@ static void pm_plls_resume(void) mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(38), ddr_data.clk_sel38 | BITS_WMSK(0x3fff, 0) | - BITS_WMSK(0x3, 14)); + BITS_WMSK(0x3u, 14)); /* uart2 */ mmio_write_32(CRU_BASE + CRU_CLKSEL_CON(18), @@ -483,7 +483,7 @@ __sramfunc void rk3328_pmic_resume(void) mmio_write_32(GPIO2_BASE, sram_data.pmic_sleep_gpio_save[0]); mmio_write_32(GPIO2_BASE + 4, sram_data.pmic_sleep_gpio_save[1]); mmio_write_32(GRF_BASE + PMIC_SLEEP_REG, - sram_data.pmic_sleep_save | BITS_WMSK(0xffff, 0)); + sram_data.pmic_sleep_save | BITS_WMSK(0xffffu, 0)); /* Resuming volt need a lot of time */ sram_udelay(100); } |