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authorMasahiro Yamada <yamada.masahiro@socionext.com>2016-12-28 16:11:41 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2017-01-18 19:33:41 +0900
commit474970535552b1e28b33461429b5492a1f1dd7cd (patch)
tree85c85f59bc891864b2b584213bffff755fdc01d8 /plat/rockchip/common/bl31_plat_setup.c
parentecdc898da3f3c01a4034d875219c61357832c12c (diff)
downloadtrusted-firmware-a-474970535552b1e28b33461429b5492a1f1dd7cd.tar.gz
Move BL_COHERENT_RAM_BASE/END defines to common_def.h
We have lots of duplicated defines (and comment blocks too). Move them to include/plat/common/common_def.h. While we are here, suffix the end address with _END instead of _LIMIT. The _END is a better fit to indicate the linker-derived real end address. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'plat/rockchip/common/bl31_plat_setup.c')
-rw-r--r--plat/rockchip/common/bl31_plat_setup.c19
1 files changed, 3 insertions, 16 deletions
diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c
index b073bde2fb..66678d3637 100644
--- a/plat/rockchip/common/bl31_plat_setup.c
+++ b/plat/rockchip/common/bl31_plat_setup.c
@@ -46,9 +46,6 @@
unsigned long __RO_START__;
unsigned long __RO_END__;
-unsigned long __COHERENT_RAM_START__;
-unsigned long __COHERENT_RAM_END__;
-
/*
* The next 2 constants identify the extents of the code & RO data region.
* These addresses are used by the MMU setup code and therefore they must be
@@ -58,16 +55,6 @@ unsigned long __COHERENT_RAM_END__;
#define BL31_RO_BASE (unsigned long)(&__RO_START__)
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
-/*
- * The next 2 constants identify the extents of the coherent memory region.
- * These addresses are used by the MMU setup code and therefore they must be
- * page-aligned. It is the responsibility of the linker script to ensure that
- * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
- * refer to page-aligned addresses.
- */
-#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
-#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
-
static entry_point_info_t bl32_ep_info;
static entry_point_info_t bl33_ep_info;
@@ -144,9 +131,9 @@ void bl31_plat_arch_setup(void)
plat_cci_init();
plat_cci_enable();
plat_configure_mmu_el3(BL31_RO_BASE,
- (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
+ BL_COHERENT_RAM_END - BL31_RO_BASE,
BL31_RO_BASE,
BL31_RO_LIMIT,
- BL31_COHERENT_RAM_BASE,
- BL31_COHERENT_RAM_LIMIT);
+ BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END);
}