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authorMarek Vasut <marek.vasut+renesas@gmail.com>2018-12-26 15:57:08 +0100
committerMarek Vasut <marek.vasut+renesas@gmail.com>2019-01-08 14:08:44 +0100
commitbc5fabd813e65967e0929d402fc437829c222564 (patch)
tree3d3010a39d1dba0219ac37c74224f87cb05919b9 /plat/renesas/rcar/bl2_plat_setup.c
parentfc181c3b2c144ba8e6c80bd45e572633a833125f (diff)
downloadtrusted-firmware-a-bc5fabd813e65967e0929d402fc437829c222564.tar.gz
rcar_gen3: plat: Fix BL2 size check
Rename BL2_LIMIT to BL2_IMAGE_LIMIT and BL2_SYSRAM_LIMIT to BL2_LIMIT to correctly set BL2_LIMIT value. Set correct DEVICE_SRAM_BASE to match the hardware. Use BL2_END in rcar_configure_mmu_el3() to mark the cacheable BL2 area. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Diffstat (limited to 'plat/renesas/rcar/bl2_plat_setup.c')
-rw-r--r--plat/renesas/rcar/bl2_plat_setup.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c
index b0ce06983b..115190dc33 100644
--- a/plat/renesas/rcar/bl2_plat_setup.c
+++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -899,7 +899,7 @@ void bl2_el3_plat_arch_setup(void)
#if RCAR_BL2_DCACHE == 1
NOTICE("BL2: D-Cache enable\n");
rcar_configure_mmu_el3(BL2_BASE,
- RCAR_SYSRAM_LIMIT - BL2_BASE,
+ BL2_END - BL2_BASE,
BL2_RO_BASE, BL2_RO_LIMIT
#if USE_COHERENT_MEM
, BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT