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author | Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> | 2020-11-30 20:39:21 +0900 |
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committer | Marek Vasut <marek.vasut+renesas@gmail.com> | 2021-07-10 17:35:20 +0200 |
commit | 0dae56bb2f0aa1f89ec98ebe3931fb19751a5c72 (patch) | |
tree | 2944241298a8539d567aab11e55bc3cb65c91cc0 /plat/renesas/common/include | |
parent | 36d5645aec947ab00b925b21141e59e58e1efd8c (diff) | |
download | trusted-firmware-a-0dae56bb2f0aa1f89ec98ebe3931fb19751a5c72.tar.gz |
fix(drivers/rcar3): fix CPG registers redefinition
This commit deletes the value of the redefined CPG register.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I05cf4a449ae28adb2ddd59593971a7d0cbcb21de
Diffstat (limited to 'plat/renesas/common/include')
-rw-r--r-- | plat/renesas/common/include/rcar_def.h | 3 | ||||
-rw-r--r-- | plat/renesas/common/include/registers/cpg_registers.h | 8 |
2 files changed, 8 insertions, 3 deletions
diff --git a/plat/renesas/common/include/rcar_def.h b/plat/renesas/common/include/rcar_def.h index 6c5b295615..93a65f1a48 100644 --- a/plat/renesas/common/include/rcar_def.h +++ b/plat/renesas/common/include/rcar_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -120,7 +120,6 @@ /* Timer control */ #define RCAR_CNTC_BASE U(0xE6080000) /* Reset */ -#define RCAR_CPGWPR U(0xE6150900) /* CPG write protect */ #define RCAR_MODEMR U(0xE6160060) /* Mode pin */ #define RCAR_CA57RESCNT U(0xE6160040) /* Reset control A57 */ #define RCAR_CA53RESCNT U(0xE6160044) /* Reset control A53 */ diff --git a/plat/renesas/common/include/registers/cpg_registers.h b/plat/renesas/common/include/registers/cpg_registers.h index 0d698d9c1b..5d2bb9e3a4 100644 --- a/plat/renesas/common/include/registers/cpg_registers.h +++ b/plat/renesas/common/include/registers/cpg_registers.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,6 +16,8 @@ #define CPG_SRCR2 (CPG_BASE + 0x00B0U) /* CPG module stop status 2 */ #define CPG_MSTPSR2 (CPG_BASE + 0x0040U) +/* CPG module stop status 2 */ +#define CPG_MSTPSR3 (CPG_BASE + 0x0048U) /* CPG write protect */ #define CPG_CPGWPR (CPG_BASE + 0x0900U) /* CPG write protect control */ @@ -24,6 +26,10 @@ #define CPG_SMSTPCR9 (CPG_BASE + 0x0994U) /* CPG module stop status 9 */ #define CPG_MSTPSR9 (CPG_BASE + 0x09A4U) +/* SDHI2 clock frequency control register */ +#define CPG_SD2CKCR (CPG_BASE + 0x0268U) +/* SDHI3 clock frequency control register */ +#define CPG_SD3CKCR (CPG_BASE + 0x026CU) /* CPG (SECURITY) registers */ |