diff options
author | Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com> | 2020-06-15 16:48:53 -0700 |
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committer | Varun Wadekar <vwadekar@nvidia.com> | 2020-08-31 10:43:44 -0700 |
commit | 3ff448f9a70254152b4debf8a52c5342052f7ebc (patch) | |
tree | 2af134725ae278c5e3c2406d27985969037de3c7 /plat/nvidia/tegra/soc | |
parent | 0da7e2dd8edbd122580b10dd6a3e53e8f4fc81b2 (diff) | |
download | trusted-firmware-a-3ff448f9a70254152b4debf8a52c5342052f7ebc.tar.gz |
Tegra: add platform specific 'runtime_setup' handler
Tegra SoCs would like the flexibility to perform chip specific actions
before we complete cold boot. This patch introduces a platform specific
'runtime_setup' handler to provide that flexibility.
Change-Id: I13b2489f631f775cae6f92acf51a240cd036ef11
Signed-off-by: Kalyani Chidambaram Vaidyanathan <kalyanic@nvidia.com>
Diffstat (limited to 'plat/nvidia/tegra/soc')
-rw-r--r-- | plat/nvidia/tegra/soc/t132/plat_setup.c | 26 | ||||
-rw-r--r-- | plat/nvidia/tegra/soc/t186/plat_setup.c | 32 | ||||
-rw-r--r-- | plat/nvidia/tegra/soc/t194/plat_setup.c | 33 | ||||
-rw-r--r-- | plat/nvidia/tegra/soc/t210/plat_setup.c | 25 |
4 files changed, 116 insertions, 0 deletions
diff --git a/plat/nvidia/tegra/soc/t132/plat_setup.c b/plat/nvidia/tegra/soc/t132/plat_setup.c index 9f9abac7fc..49e8b5d885 100644 --- a/plat/nvidia/tegra/soc/t132/plat_setup.c +++ b/plat/nvidia/tegra/soc/t132/plat_setup.c @@ -173,3 +173,29 @@ bool plat_supports_system_suspend(void) { return true; } + +/******************************************************************************* + * Platform specific runtime setup. + ******************************************************************************/ +void plat_runtime_setup(void) +{ + /* + * During cold boot, it is observed that the arbitration + * bit is set in the Memory controller leading to false + * error interrupts in the non-secure world. To avoid + * this, clean the interrupt status register before + * booting into the non-secure world + */ + tegra_memctrl_clear_pending_interrupts(); + + /* + * During boot, USB3 and flash media (SDMMC/SATA) devices need + * access to IRAM. Because these clients connect to the MC and + * do not have a direct path to the IRAM, the MC implements AHB + * redirection during boot to allow path to IRAM. In this mode + * accesses to a programmed memory address aperture are directed + * to the AHB bus, allowing access to the IRAM. This mode must be + * disabled before we jump to the non-secure world. + */ + tegra_memctrl_disable_ahb_redirection(); +} diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c index ab374a4e05..d6d090aba2 100644 --- a/plat/nvidia/tegra/soc/t186/plat_setup.c +++ b/plat/nvidia/tegra/soc/t186/plat_setup.c @@ -27,6 +27,7 @@ #include <mce.h> #include <memctrl.h> +#include <smmu.h> #include <tegra_def.h> #include <tegra_platform.h> #include <tegra_private.h> @@ -363,3 +364,34 @@ bool plat_supports_system_suspend(void) { return true; } +/******************************************************************************* + * Platform specific runtime setup. + ******************************************************************************/ +void plat_runtime_setup(void) +{ + /* + * During cold boot, it is observed that the arbitration + * bit is set in the Memory controller leading to false + * error interrupts in the non-secure world. To avoid + * this, clean the interrupt status register before + * booting into the non-secure world + */ + tegra_memctrl_clear_pending_interrupts(); + + /* + * During boot, USB3 and flash media (SDMMC/SATA) devices need + * access to IRAM. Because these clients connect to the MC and + * do not have a direct path to the IRAM, the MC implements AHB + * redirection during boot to allow path to IRAM. In this mode + * accesses to a programmed memory address aperture are directed + * to the AHB bus, allowing access to the IRAM. This mode must be + * disabled before we jump to the non-secure world. + */ + tegra_memctrl_disable_ahb_redirection(); + + /* + * Verify the integrity of the previously configured SMMU(s) + * settings + */ + tegra_smmu_verify(); +} diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c index 1998e9c601..8f7d1e9a19 100644 --- a/plat/nvidia/tegra/soc/t194/plat_setup.c +++ b/plat/nvidia/tegra/soc/t194/plat_setup.c @@ -20,7 +20,9 @@ #include <bl31/interrupt_mgmt.h> #include <mce.h> #include <mce_private.h> +#include <memctrl.h> #include <plat/common/platform.h> +#include <smmu.h> #include <spe.h> #include <tegra_def.h> #include <tegra_platform.h> @@ -414,3 +416,34 @@ bool plat_supports_system_suspend(void) { return true; } + +/******************************************************************************* + * Platform specific runtime setup. + ******************************************************************************/ +void plat_runtime_setup(void) +{ + /* + * During cold boot, it is observed that the arbitration + * bit is set in the Memory controller leading to false + * error interrupts in the non-secure world. To avoid + * this, clean the interrupt status register before + * booting into the non-secure world + */ + tegra_memctrl_clear_pending_interrupts(); + + /* + * During boot, USB3 and flash media (SDMMC/SATA) devices need + * access to IRAM. Because these clients connect to the MC and + * do not have a direct path to the IRAM, the MC implements AHB + * redirection during boot to allow path to IRAM. In this mode + * accesses to a programmed memory address aperture are directed + * to the AHB bus, allowing access to the IRAM. This mode must be + * disabled before we jump to the non-secure world. + */ + tegra_memctrl_disable_ahb_redirection(); + + /* + * Verify the integrity of the previously configured SMMU(s) settings + */ + tegra_smmu_verify(); +} diff --git a/plat/nvidia/tegra/soc/t210/plat_setup.c b/plat/nvidia/tegra/soc/t210/plat_setup.c index 20dde3b9c5..68cd38ec3b 100644 --- a/plat/nvidia/tegra/soc/t210/plat_setup.c +++ b/plat/nvidia/tegra/soc/t210/plat_setup.c @@ -291,3 +291,28 @@ bool plat_supports_system_suspend(void) return false; } } +/******************************************************************************* + * Platform specific runtime setup. + ******************************************************************************/ +void plat_runtime_setup(void) +{ + /* + * During cold boot, it is observed that the arbitration + * bit is set in the Memory controller leading to false + * error interrupts in the non-secure world. To avoid + * this, clean the interrupt status register before + * booting into the non-secure world + */ + tegra_memctrl_clear_pending_interrupts(); + + /* + * During boot, USB3 and flash media (SDMMC/SATA) devices need + * access to IRAM. Because these clients connect to the MC and + * do not have a direct path to the IRAM, the MC implements AHB + * redirection during boot to allow path to IRAM. In this mode + * accesses to a programmed memory address aperture are directed + * to the AHB bus, allowing access to the IRAM. This mode must be + * disabled before we jump to the non-secure world. + */ + tegra_memctrl_disable_ahb_redirection(); +} |