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authorVarun Wadekar <vwadekar@nvidia.com>2019-08-22 11:52:36 -0700
committerManish Pandey <manish.pandey2@arm.com>2020-08-24 21:27:14 +0000
commit13fed5a7b4eff961a61259a0978d567d062b14fb (patch)
tree18c8756531c203697f16cae9907b46bb73fe2dc5 /plat/nvidia/tegra/soc
parentf41dc86c1eeaa835e85ed576aae6fef056b0861b (diff)
downloadtrusted-firmware-a-13fed5a7b4eff961a61259a0978d567d062b14fb.tar.gz
Tegra: TZDRAM setup from soc specific early_boot handlers
TZDRAM setup is not required for all Tegra SoCs. The previous bootloader can enable the TZDRAM fence due to architectural improvements in the newer chips. This patch moves the TZDRAM setup to early_boot handlers for SoCs to handle this scenario. Change-Id: I6481b4f848a4dadc20cb83852cd8e19a242b3a34 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'plat/nvidia/tegra/soc')
-rw-r--r--plat/nvidia/tegra/soc/t132/plat_setup.c9
-rw-r--r--plat/nvidia/tegra/soc/t186/plat_setup.c15
-rw-r--r--plat/nvidia/tegra/soc/t210/plat_setup.c6
3 files changed, 30 insertions, 0 deletions
diff --git a/plat/nvidia/tegra/soc/t132/plat_setup.c b/plat/nvidia/tegra/soc/t132/plat_setup.c
index f7b134d15f..9f9abac7fc 100644
--- a/plat/nvidia/tegra/soc/t132/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t132/plat_setup.c
@@ -10,6 +10,7 @@
#include <common/bl_common.h>
#include <drivers/console.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <memctrl.h>
#include <plat/common/platform.h>
#include <tegra_def.h>
#include <tegra_platform.h>
@@ -145,8 +146,16 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
******************************************************************************/
void plat_early_platform_setup(void)
{
+ plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
+
/* Verify chip id is t132 */
assert(tegra_chipid_is_t132());
+
+ /*
+ * Do initial security configuration to allow DRAM/device access.
+ */
+ tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
+ (uint32_t)plat_params->tzdram_size);
}
/*******************************************************************************
diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c
index 03182d789a..ab374a4e05 100644
--- a/plat/nvidia/tegra/soc/t186/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t186/plat_setup.c
@@ -26,6 +26,7 @@
#include <plat/common/platform.h>
#include <mce.h>
+#include <memctrl.h>
#include <tegra_def.h>
#include <tegra_platform.h>
#include <tegra_private.h>
@@ -185,6 +186,7 @@ void plat_early_platform_setup(void)
{
uint64_t impl, val;
const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
+ const struct tegra_bl31_params *arg_from_bl2 = plat_get_bl31_params();
/* Verify chip id is t186 */
assert(tegra_chipid_is_t186());
@@ -192,6 +194,12 @@ void plat_early_platform_setup(void)
/* sanity check MCE firmware compatibility */
mce_verify_firmware_version();
+ /*
+ * Do initial security configuration to allow DRAM/device access.
+ */
+ tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
+ (uint32_t)plat_params->tzdram_size);
+
impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK;
/*
@@ -205,6 +213,13 @@ void plat_early_platform_setup(void)
val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
write_l2ctlr_el1(val);
}
+
+ /*
+ * The previous bootloader might not have placed the BL32 image
+ * inside the TZDRAM. Platform handler to allow relocation of BL32
+ * image to TZDRAM memory. This behavior might change per platform.
+ */
+ plat_relocate_bl32_image(arg_from_bl2->bl32_image_info);
}
/*******************************************************************************
diff --git a/plat/nvidia/tegra/soc/t210/plat_setup.c b/plat/nvidia/tegra/soc/t210/plat_setup.c
index a16f302a69..20dde3b9c5 100644
--- a/plat/nvidia/tegra/soc/t210/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t210/plat_setup.c
@@ -168,6 +168,12 @@ void plat_early_platform_setup(void)
/* Verify chip id is t210 */
assert(tegra_chipid_is_t210());
+ /*
+ * Do initial security configuration to allow DRAM/device access.
+ */
+ tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
+ (uint32_t)plat_params->tzdram_size);
+
/* platform parameter passed by the previous bootloader */
if (plat_params->l2_ecc_parity_prot_dis != 1) {
/* Enable ECC Parity Protection for Cortex-A57 CPUs */