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authorkalyani chidambaram <kalyanic@nvidia.com>2018-04-09 15:18:02 -0700
committerVarun Wadekar <vwadekar@nvidia.com>2020-02-20 09:25:45 -0800
commit37f760241e75bbfa5c4043f9e451fc0ce7ed42f7 (patch)
treee1479f1f3f5f40ab0b51a0758ac1a1b89cee8e03 /plat/nvidia/tegra/soc/t210
parentdd4f0885a0aad2af6d873c00ac5b49e166c5e339 (diff)
downloadtrusted-firmware-a-37f760241e75bbfa5c4043f9e451fc0ce7ed42f7.tar.gz
Tegra210: secure PMC hardware block
This patch sets the "secure" bit to mark the PMC hardware block as accessible only from the secure world. This setting must be programmed during cold boot and System Resume. The sc7entry-fw, running on the COP, needs access to the PMC block to enter System Suspend state, so "unlock" the PMC block before passing control to the COP. Change-Id: I00e39a49ae6b9f8c8eafe0cf7ff63fe6a67fdccf Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>
Diffstat (limited to 'plat/nvidia/tegra/soc/t210')
-rw-r--r--plat/nvidia/tegra/soc/t210/plat_psci_handlers.c13
-rw-r--r--plat/nvidia/tegra/soc/t210/plat_setup.c7
2 files changed, 19 insertions, 1 deletions
diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
index 295a9a9cef..832b8d647f 100644
--- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
@@ -394,6 +394,15 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
*/
tegra_reset_all_dma_masters();
+ /*
+ * Mark PMC as accessible to the non-secure world
+ * to allow the COP to execute System Suspend
+ * sequence
+ */
+ val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
+ val &= ~PMC_SECURITY_EN_BIT;
+ mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
+
/* clean up IRAM of any cruft */
zeromem((void *)(uintptr_t)TEGRA_IRAM_BASE,
TEGRA_IRAM_A_SIZE);
@@ -480,12 +489,14 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
tegra_bpmp_resume();
}
- /* sc7entry-fw is part of TZDRAM area */
if (plat_params->sc7entry_fw_base != 0U) {
+ /* sc7entry-fw is part of TZDRAM area */
offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base;
tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base,
plat_params->tzdram_size + offset);
+ }
+ if (!tegra_chipid_is_t210_b01()) {
/* restrict PMC access to secure world */
val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
val |= PMC_SECURITY_EN_BIT;
diff --git a/plat/nvidia/tegra/soc/t210/plat_setup.c b/plat/nvidia/tegra/soc/t210/plat_setup.c
index da1f1b33eb..c4bd58e33b 100644
--- a/plat/nvidia/tegra/soc/t210/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t210/plat_setup.c
@@ -236,6 +236,13 @@ void plat_late_platform_setup(void)
val |= PMC_SECURITY_EN_BIT;
mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
}
+
+ if (!tegra_chipid_is_t210_b01()) {
+ /* restrict PMC access to secure world */
+ val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
+ val |= PMC_SECURITY_EN_BIT;
+ mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
+ }
}
/*******************************************************************************