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authorVarun Wadekar <vwadekar@nvidia.com>2015-11-09 17:39:28 -0800
committerVarun Wadekar <vwadekar@nvidia.com>2015-11-10 09:25:28 -0800
commit3b40f993f40e1299edcea8ab662df5a2f518e89c (patch)
treed4d6d72d1c12b3840df4d1eb576960c7b69a9d83 /plat/nvidia/tegra/soc/t132
parent4266228306de468dff34609581474f2f43d781fa (diff)
downloadtrusted-firmware-a-3b40f993f40e1299edcea8ab662df5a2f518e89c.tar.gz
Tegra: introduce per-soc system reset handler
This patch adds a per-soc system reset handler for Tegra chips. The handler gets executed before the actual system resets. This allows for custom handling of the system reset sequence on each SoC. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'plat/nvidia/tegra/soc/t132')
-rw-r--r--plat/nvidia/tegra/soc/t132/plat_psci_handlers.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
index 79e9f1c507..46e594096f 100644
--- a/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
@@ -33,6 +33,7 @@
#include <assert.h>
#include <denver.h>
#include <debug.h>
+#include <delay_timer.h>
#include <flowctrl.h>
#include <mmio.h>
#include <platform_def.h>
@@ -48,6 +49,11 @@
#define CPU_CMPLX_RESET_CLR 0x344
#define CPU_CORE_RESET_MASK 0x10001
+/* Clock and Reset controller registers for system clock's settings */
+#define SCLK_RATE 0x30
+#define SCLK_BURST_POLICY 0x28
+#define SCLK_BURST_POLICY_DEFAULT 0x10000000
+
static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
int32_t tegra_soc_validate_power_state(unsigned int power_state)
@@ -121,3 +127,19 @@ int tegra_soc_prepare_cpu_suspend(unsigned int id, unsigned int afflvl)
return PSCI_E_SUCCESS;
}
+
+int tegra_soc_prepare_system_reset(void)
+{
+ /*
+ * Set System Clock (SCLK) to POR default so that the clock source
+ * for the PMC APB clock would not be changed due to system reset.
+ */
+ mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY,
+ SCLK_BURST_POLICY_DEFAULT);
+ mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0);
+
+ /* Wait 1 ms to make sure clock source/device logic is stabilized. */
+ mdelay(1);
+
+ return PSCI_E_SUCCESS;
+}