diff options
author | Yidi Lin <yidi.lin@mediatek.com> | 2020-12-10 19:56:50 +0800 |
---|---|---|
committer | Yidi Lin <yidi.lin@mediatek.com> | 2020-12-16 17:22:02 +0800 |
commit | 04589e2b1e5eca4efbf032907879221c34e35c84 (patch) | |
tree | 431a68efae826d45e68f546bcedda5ace7b6c557 /plat/mediatek | |
parent | 42f2fa823fe5ecd2eba0e7141c05859153a49581 (diff) | |
download | trusted-firmware-a-04589e2b1e5eca4efbf032907879221c34e35c84.tar.gz |
mediatek: mt8192: Fix non-MISRA compliant code
CID 364144: Integer handling issues (NO_EFFECT)
The unsigned value is always greater-than-or-equal-to-zero.
Remove such check.
Change-Id: Ia395eb32f55a7098d2581ce7f548b7e1112beaa0
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Diffstat (limited to 'plat/mediatek')
-rw-r--r-- | plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_main.c | 29 |
1 files changed, 14 insertions, 15 deletions
diff --git a/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_main.c b/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_main.c index 053d21081b..f1d8493863 100644 --- a/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_main.c +++ b/plat/mediatek/mt8192/drivers/ptp3/mtk_ptp3_main.c @@ -39,15 +39,15 @@ void ptp3_init(unsigned int core) { unsigned int _core; - if (core >= PTP3_CFG1_CPU_START_ID) { - if (core < NR_PTP3_CFG1_CPU) { - /* update ptp3_cfg1 */ - ptp3_write( - ptp3_cfg1[core][PTP3_CFG_ADDR], - ptp3_cfg1[core][PTP3_CFG_VALUE]); - } + /* Apply ptp3_cfg1 for core 0 to 7 */ + if (core < NR_PTP3_CFG1_CPU) { + /* update ptp3_cfg1 */ + ptp3_write( + ptp3_cfg1[core][PTP3_CFG_ADDR], + ptp3_cfg1[core][PTP3_CFG_VALUE]); } + /* Apply ptp3_cfg2 for core 4 to 7 */ if (core >= PTP3_CFG2_CPU_START_ID) { _core = core - PTP3_CFG2_CPU_START_ID; @@ -59,6 +59,7 @@ void ptp3_init(unsigned int core) } } + /* Apply ptp3_cfg3 for core 4 to 7 */ if (core >= PTP3_CFG3_CPU_START_ID) { _core = core - PTP3_CFG3_CPU_START_ID; @@ -73,13 +74,11 @@ void ptp3_init(unsigned int core) void ptp3_deinit(unsigned int core) { - if (core >= PTP3_CFG1_CPU_START_ID) { - if (core < NR_PTP3_CFG1_CPU) { - /* update ptp3_cfg1 */ - ptp3_write( - ptp3_cfg1[core][PTP3_CFG_ADDR], - ptp3_cfg1[core][PTP3_CFG_VALUE] & - ~PTP3_CFG1_MASK); - } + if (core < NR_PTP3_CFG1_CPU) { + /* update ptp3_cfg1 */ + ptp3_write( + ptp3_cfg1[core][PTP3_CFG_ADDR], + ptp3_cfg1[core][PTP3_CFG_VALUE] & + ~PTP3_CFG1_MASK); } } |