diff options
author | Konstantin Porotchkin <kostap@marvell.com> | 2019-03-31 17:22:53 +0300 |
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committer | Marcin Wojtas <mw@semihalf.com> | 2020-06-19 17:59:44 +0200 |
commit | c96aa7fb3d9b306d50d71659a3c3d036ac9e3673 (patch) | |
tree | 9161731485cbe3db3e07b869b492b133821dc90c /plat/marvell/armada | |
parent | 957a5add638b1269210eac3a655e6b15e6fdb92e (diff) | |
download | trusted-firmware-a-c96aa7fb3d9b306d50d71659a3c3d036ac9e3673.tar.gz |
plat: marvell: armada: a8k: check CCU window state before loading MSS BL2
Make sure the current CCU window is not in use before adding
a new address map during MSS BL2 image load preparations.
At BL2 stage the CCU Win-2 points to DRAM. If additional mapping is
added to MSS BL2 stage initialization, the DDR entry will be destroyed
and lead to the system hang.
Change-Id: I215e83508acc37d54dab6954d791b9a74cc883ca
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Diffstat (limited to 'plat/marvell/armada')
-rw-r--r-- | plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c b/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c index cdbae9df18..c2cd933578 100644 --- a/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c +++ b/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c @@ -63,10 +63,15 @@ static int bl2_plat_mmap_init(void) * Do not touch CCU window 0, * it's used for the internal registers access */ - for (cfg_idx = 0, win_id = 1; cfg_idx < cfg_num; cfg_idx++, win_id++) { + for (cfg_idx = 0, win_id = 1; + (win_id < MVEBU_CCU_MAX_WINS) && (cfg_idx < cfg_num); win_id++) { + /* Skip already enabled CCU windows */ + if (ccu_is_win_enabled(MVEBU_AP0, win_id)) + continue; /* Enable required CCU windows */ ccu_win_check(&ccu_mem_map[cfg_idx]); ccu_enable_win(MVEBU_AP0, &ccu_mem_map[cfg_idx], win_id); + cfg_idx++; } /* Config address for each cp other than cp0 */ |