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author | Konstantin Porotchkin <kostap@marvell.com> | 2019-04-15 16:32:59 +0300 |
---|---|---|
committer | Manish Pandey <manish.pandey2@arm.com> | 2020-07-10 10:55:23 +0000 |
commit | 0a977b9b8bfc0356830d88e3602e2e5ef4a1ac06 (patch) | |
tree | 1498cdc26f4ee8bd08c64e464c2b2738bdfa2d65 /plat/marvell/armada | |
parent | 0eb3d1fc75e3929d2a29a934bdbe858177b26e07 (diff) | |
download | trusted-firmware-a-0a977b9b8bfc0356830d88e3602e2e5ef4a1ac06.tar.gz |
plat: marvell: armada: a8k: change CCU LLC SRAM mapping
The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage.
The CCU have to prepare SRAM window, but point to the DRAM-0 target
until the SRAM is actually enabled.
This patch changes CCU SRAM window target to DRAM-0
Remove dependence between LLC_SRAM and LLC_ENABLE and update the
build documentation.
The SRAМ base moved to follow the OP-TEE SHMEM area (0x05400000)
Change-Id: I85c2434a3d515ec37da5ae8eb729e3280f91c456
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Diffstat (limited to 'plat/marvell/armada')
6 files changed, 19 insertions, 15 deletions
diff --git a/plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c b/plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c index 7d30ebe5a7..a409261029 100644 --- a/plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c +++ b/plat/marvell/armada/a8k/a70x0/board/marvell_plat_config.c @@ -103,7 +103,10 @@ struct addr_map_win ccu_memory_map[] = { /* IO window */ {0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */ #else #if LLC_SRAM - {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, SRAM_TID}, + /* This entry is prepared for OP-TEE OS that enables the LLC SRAM + * and changes the window target to SRAM_TID. + */ + {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID}, #endif {0x00000000f2000000, 0xe000000, IO_0_TID}, {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */ diff --git a/plat/marvell/armada/a8k/a70x0_amc/board/marvell_plat_config.c b/plat/marvell/armada/a8k/a70x0_amc/board/marvell_plat_config.c index 7fc33f1f90..3b68e91ba0 100644 --- a/plat/marvell/armada/a8k/a70x0_amc/board/marvell_plat_config.c +++ b/plat/marvell/armada/a8k/a70x0_amc/board/marvell_plat_config.c @@ -94,7 +94,10 @@ struct addr_map_win ccu_memory_map[] = { {0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */ #else #if LLC_SRAM - {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, SRAM_TID}, + /* This entry is prepared for OP-TEE OS that enables the LLC SRAM + * and changes the window target to SRAM_TID. + */ + {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID}, #endif {0x00000000f2000000, 0xe000000, IO_0_TID}, {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */ diff --git a/plat/marvell/armada/a8k/a80x0/board/marvell_plat_config.c b/plat/marvell/armada/a8k/a80x0/board/marvell_plat_config.c index 856c07a6e3..4ccda14e95 100644 --- a/plat/marvell/armada/a8k/a80x0/board/marvell_plat_config.c +++ b/plat/marvell/armada/a8k/a80x0/board/marvell_plat_config.c @@ -132,7 +132,10 @@ struct addr_map_win ccu_memory_map[] = { {0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */ #else #if LLC_SRAM - {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, SRAM_TID}, + /* This entry is prepared for OP-TEE OS that enables the LLC SRAM + * and changes the window target to SRAM_TID. + */ + {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID}, #endif {0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */ {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */ diff --git a/plat/marvell/armada/a8k/a80x0_mcbin/board/marvell_plat_config.c b/plat/marvell/armada/a8k/a80x0_mcbin/board/marvell_plat_config.c index 0edc977458..b9329675f0 100644 --- a/plat/marvell/armada/a8k/a80x0_mcbin/board/marvell_plat_config.c +++ b/plat/marvell/armada/a8k/a80x0_mcbin/board/marvell_plat_config.c @@ -166,7 +166,10 @@ struct addr_map_win ccu_memory_map[] = { {0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */ #else #if LLC_SRAM - {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, SRAM_TID}, + /* This entry is prepared for OP-TEE OS that enables the LLC SRAM + * and changes the window target to SRAM_TID. + */ + {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID}, #endif {0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */ {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */ diff --git a/plat/marvell/armada/a8k/common/include/platform_def.h b/plat/marvell/armada/a8k/common/include/platform_def.h index cbef3a173c..944a1517ba 100644 --- a/plat/marvell/armada/a8k/common/include/platform_def.h +++ b/plat/marvell/armada/a8k/common/include/platform_def.h @@ -96,13 +96,13 @@ #define PLAT_MARVELL_TRUSTED_ROM_BASE PLAT_MARVELL_ATF_LOAD_ADDR /* 4 MB for FIP image */ #define PLAT_MARVELL_TRUSTED_ROM_SIZE 0x00400000 -/* Reserve 12M for SCP (Secure PayLoad) Trusted RAM - * OP-TEE SHMEM follows this region +/* Reserve 12MB for SCP (Secure PayLoad) Trusted RAM + * OP-TEE 4MB SHMEM follows this region */ #define PLAT_MARVELL_TRUSTED_RAM_BASE 0x04400000 #define PLAT_MARVELL_TRUSTED_RAM_SIZE 0x00C00000 /* 12 MB DRAM */ -#define PLAT_MARVELL_LLC_SRAM_BASE PLAT_MARVELL_TRUSTED_RAM_BASE +#define PLAT_MARVELL_LLC_SRAM_BASE 0x05400000 #define PLAT_MARVELL_LLC_SRAM_SIZE 0x00100000 /* 1 MB SRAM */ /* diff --git a/plat/marvell/armada/common/marvell_common.mk b/plat/marvell/armada/common/marvell_common.mk index fcc97acd36..5c8c7db2d7 100644 --- a/plat/marvell/armada/common/marvell_common.mk +++ b/plat/marvell/armada/common/marvell_common.mk @@ -22,15 +22,7 @@ LLC_SRAM := 0 $(eval $(call add_define,LLC_SRAM)) # Enable/Disable LLC -ifeq (${LLC_SRAM}, 0) LLC_ENABLE := 1 -else -# When LLC_SRAM=1, the entire LLC converted to SRAM and enabled at BL1. -# All existing cases activating LLC at BL31 stage should be disabled. -# The below assignment does not allow changing the LLC_ENABLE -# value in the command line. -LLC_ENABLE = 0 -endif $(eval $(call add_define,LLC_ENABLE)) include lib/xlat_tables_v2/xlat_tables.mk |