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authorGrzegorz Jaszczyk <jaz@semihalf.com>2019-11-05 13:14:59 +0100
committerMarcin Wojtas <mw@semihalf.com>2020-06-07 00:06:03 +0200
commita28471722afb3ae784d7bce2118c2ea703f8444c (patch)
tree60edc1ee925bc6645747b23d6621ed9a862a4e39 /plat/marvell/a8k/a80x0
parent967a6d162d9dc1c5ae154f289bcdecc03cb9eb7c (diff)
downloadtrusted-firmware-a-a28471722afb3ae784d7bce2118c2ea703f8444c.tar.gz
marvell: armada: add extra level in marvell platform hierarchy
This commit is a preparation for upcoming support for OcteonTX and OcteonTX2 product families. Armada platform related files (docs, plat, include/plat) are moved to the new "armada" sub-folder. Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Diffstat (limited to 'plat/marvell/a8k/a80x0')
-rw-r--r--plat/marvell/a8k/a80x0/board/dram_port.c142
-rw-r--r--plat/marvell/a8k/a80x0/board/marvell_plat_config.c196
-rw-r--r--plat/marvell/a8k/a80x0/board/phy-porting-layer.h181
-rw-r--r--plat/marvell/a8k/a80x0/mvebu_def.h17
-rw-r--r--plat/marvell/a8k/a80x0/platform.mk20
5 files changed, 0 insertions, 556 deletions
diff --git a/plat/marvell/a8k/a80x0/board/dram_port.c b/plat/marvell/a8k/a80x0/board/dram_port.c
deleted file mode 100644
index 02f4ffb0a3..0000000000
--- a/plat/marvell/a8k/a80x0/board/dram_port.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright (C) 2018 Marvell International Ltd.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- * https://spdx.org/licenses
- */
-
-#include <arch_helpers.h>
-#include <common/debug.h>
-#include <drivers/mentor/mi2cv.h>
-#include <lib/mmio.h>
-
-#include <mv_ddr_if.h>
-#include <mvebu_def.h>
-#include <plat_marvell.h>
-
-#define MVEBU_AP_MPP_CTRL0_7_REG MVEBU_AP_MPP_REGS(0)
-#define MVEBU_AP_MPP_CTRL4_OFFS 16
-#define MVEBU_AP_MPP_CTRL5_OFFS 20
-#define MVEBU_AP_MPP_CTRL4_I2C0_SDA_ENA 0x3
-#define MVEBU_AP_MPP_CTRL5_I2C0_SCK_ENA 0x3
-
-#define MVEBU_CP_MPP_CTRL37_OFFS 20
-#define MVEBU_CP_MPP_CTRL38_OFFS 24
-#define MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA 0x2
-#define MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA 0x2
-
-#define MVEBU_MPP_CTRL_MASK 0xf
-
-/*
- * This struct provides the DRAM training code with
- * the appropriate board DRAM configuration
- */
-static struct mv_ddr_topology_map board_topology_map = {
- /* MISL board with 1CS 8Gb x4 devices of Micron 2400T */
- DEBUG_LEVEL_ERROR,
- 0x1, /* active interfaces */
- /* cs_mask, mirror, dqs_swap, ck_swap X subphys */
- { { { {0x1, 0x0, 0, 0}, /* FIXME: change the cs mask for all 64 bit */
- {0x1, 0x0, 0, 0},
- {0x1, 0x0, 0, 0},
- {0x1, 0x0, 0, 0},
- {0x1, 0x0, 0, 0},
- {0x1, 0x0, 0, 0},
- {0x1, 0x0, 0, 0},
- {0x1, 0x0, 0, 0},
- {0x1, 0x0, 0, 0} },
- /* TODO: double check if the speed bin is 2400T */
- SPEED_BIN_DDR_2400T, /* speed_bin */
- MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */
- MV_DDR_DIE_CAP_8GBIT, /* die capacity */
- MV_DDR_FREQ_SAR, /* frequency */
- 0, 0, /* cas_l, cas_wl */
- MV_DDR_TEMP_LOW} }, /* temperature */
- MV_DDR_64BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
- MV_DDR_CFG_SPD, /* ddr configuration data source */
- { {0} }, /* raw spd data */
- {0}, /* timing parameters */
- { /* electrical configuration */
- { /* memory electrical configuration */
- MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
- {
- MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */
- MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */
- },
- {
- MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */
- MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */
- },
- MV_DDR_DIC_RZQ_DIV7 /* dic */
- },
- { /* phy electrical configuration */
- MV_DDR_OHM_30, /* data_drv_p */
- MV_DDR_OHM_30, /* data_drv_n */
- MV_DDR_OHM_30, /* ctrl_drv_p */
- MV_DDR_OHM_30, /* ctrl_drv_n */
- {
- MV_DDR_OHM_60, /* odt_p 1cs */
- MV_DDR_OHM_120 /* odt_p 2cs */
- },
- {
- MV_DDR_OHM_60, /* odt_n 1cs */
- MV_DDR_OHM_120 /* odt_n 2cs */
- },
- },
- { /* mac electrical configuration */
- MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
- MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
- MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
- },
- }
-};
-
-struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
-{
- /* Return the board topology as defined in the board code */
- return &board_topology_map;
-}
-
-static void mpp_config(void)
-{
- uintptr_t reg;
- uint32_t val;
-
- reg = MVEBU_CP_MPP_REGS(0, 4);
- /* configure CP0 MPP 37 and 38 to i2c */
- val = mmio_read_32(reg);
- val &= ~((MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL37_OFFS) |
- (MVEBU_MPP_CTRL_MASK << MVEBU_CP_MPP_CTRL38_OFFS));
- val |= (MVEBU_CP_MPP_CTRL37_I2C0_SCK_ENA <<
- MVEBU_CP_MPP_CTRL37_OFFS) |
- (MVEBU_CP_MPP_CTRL38_I2C0_SDA_ENA <<
- MVEBU_CP_MPP_CTRL38_OFFS);
- mmio_write_32(reg, val);
-}
-
-/*
- * This function may modify the default DRAM parameters
- * based on information received from SPD or bootloader
- * configuration located on non volatile storage
- */
-void plat_marvell_dram_update_topology(void)
-{
- struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
-
- INFO("Gathering DRAM information\n");
-
- if (tm->cfg_src == MV_DDR_CFG_SPD) {
- /* configure MPPs to enable i2c */
- mpp_config();
-
- /* initialize i2c */
- i2c_init((void *)MVEBU_CP0_I2C_BASE);
-
- /* select SPD memory page 0 to access DRAM configuration */
- i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 1);
-
- /* read data from spd */
- i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,
- sizeof(tm->spd_data.all_bytes));
- }
-}
diff --git a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0/board/marvell_plat_config.c
deleted file mode 100644
index 7901dd225c..0000000000
--- a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * Copyright (C) 2018 Marvell International Ltd.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- * https://spdx.org/licenses
- */
-
-#include <armada_common.h>
-
-/*
- * If bootrom is currently at BLE there's no need to include the memory
- * maps structure at this point
- */
-#include <mvebu_def.h>
-#ifndef IMAGE_BLE
-
-/*****************************************************************************
- * AMB Configuration
- *****************************************************************************
- */
-struct addr_map_win amb_memory_map[] = {
- /* CP1 SPI1 CS0 Direct Mode access */
- {0xf900, 0x1000000, AMB_SPI1_CS0_ID},
-};
-
-int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size,
- uintptr_t base)
-{
- *win = amb_memory_map;
- if (*win == NULL)
- *size = 0;
- else
- *size = ARRAY_SIZE(amb_memory_map);
-
- return 0;
-}
-#endif
-
-/*****************************************************************************
- * IO WIN Configuration
- *****************************************************************************
- */
-struct addr_map_win io_win_memory_map[] = {
- /* CP1 (MCI0) internal regs */
- {0x00000000f4000000, 0x2000000, MCI_0_TID},
-#ifndef IMAGE_BLE
- /* PCIe0 and SPI1_CS0 (RUNIT) on CP1*/
- {0x00000000f9000000, 0x2000000, MCI_0_TID},
- /* PCIe1 on CP1*/
- {0x00000000fb000000, 0x1000000, MCI_0_TID},
- /* PCIe2 on CP1*/
- {0x00000000fc000000, 0x1000000, MCI_0_TID},
- /* MCI 0 indirect window */
- {MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID},
- /* MCI 1 indirect window */
- {MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID},
-#endif
-};
-
-uint32_t marvell_get_io_win_gcr_target(int ap_index)
-{
- return PIDI_TID;
-}
-
-int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win,
- uint32_t *size)
-{
- *win = io_win_memory_map;
- if (*win == NULL)
- *size = 0;
- else
- *size = ARRAY_SIZE(io_win_memory_map);
-
- return 0;
-}
-
-#ifndef IMAGE_BLE
-/*****************************************************************************
- * IOB Configuration
- *****************************************************************************
- */
-struct addr_map_win iob_memory_map_cp0[] = {
- /* CP0 */
- /* PEX1_X1 window */
- {0x00000000f7000000, 0x1000000, PEX1_TID},
- /* PEX2_X1 window */
- {0x00000000f8000000, 0x1000000, PEX2_TID},
- /* PEX0_X4 window */
- {0x00000000f6000000, 0x1000000, PEX0_TID},
- {0x00000000c0000000, 0x30000000, PEX0_TID},
- {0x0000000800000000, 0x100000000, PEX0_TID},
-};
-
-struct addr_map_win iob_memory_map_cp1[] = {
- /* CP1 */
- /* SPI1_CS0 (RUNIT) window */
- {0x00000000f9000000, 0x1000000, RUNIT_TID},
- /* PEX1_X1 window */
- {0x00000000fb000000, 0x1000000, PEX1_TID},
- /* PEX2_X1 window */
- {0x00000000fc000000, 0x1000000, PEX2_TID},
- /* PEX0_X4 window */
- {0x00000000fa000000, 0x1000000, PEX0_TID}
-};
-
-int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size,
- uintptr_t base)
-{
- switch (base) {
- case MVEBU_CP_REGS_BASE(0):
- *win = iob_memory_map_cp0;
- *size = ARRAY_SIZE(iob_memory_map_cp0);
- return 0;
- case MVEBU_CP_REGS_BASE(1):
- *win = iob_memory_map_cp1;
- *size = ARRAY_SIZE(iob_memory_map_cp1);
- return 0;
- default:
- *size = 0;
- *win = 0;
- return 1;
- }
-}
-#endif
-
-/*****************************************************************************
- * CCU Configuration
- *****************************************************************************
- */
-struct addr_map_win ccu_memory_map[] = {
-#ifdef IMAGE_BLE
- {0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
-#else
- {0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */
- {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
- {0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */
-#endif
-};
-
-uint32_t marvell_get_ccu_gcr_target(int ap)
-{
- return DRAM_0_TID;
-}
-
-int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win,
- uint32_t *size)
-{
- *win = ccu_memory_map;
- *size = ARRAY_SIZE(ccu_memory_map);
-
- return 0;
-}
-
-#ifndef IMAGE_BLE
-/*****************************************************************************
- * SoC PM configuration
- *****************************************************************************
- */
-/* CP GPIO should be used and the GPIOs should be within same GPIO register */
-struct power_off_method pm_cfg = {
- .type = PMIC_GPIO,
- .cfg.gpio.pin_count = 1,
- .cfg.gpio.info = {{0, 35} },
- .cfg.gpio.step_count = 7,
- .cfg.gpio.seq = {1, 0, 1, 0, 1, 0, 1},
- .cfg.gpio.delay_ms = 10,
-};
-
-void *plat_marvell_get_pm_cfg(void)
-{
- /* Return the PM configurations */
- return &pm_cfg;
-}
-
-/* In reference to #ifndef IMAGE_BLE, this part is used for BLE only. */
-#else
-/*****************************************************************************
- * SKIP IMAGE Configuration
- *****************************************************************************
- */
-#if PLAT_RECOVERY_IMAGE_ENABLE
-struct skip_image skip_im = {
- .detection_method = GPIO,
- .info.gpio.num = 33,
- .info.gpio.button_state = HIGH,
- .info.test.cp_ap = CP,
- .info.test.cp_index = 0,
-};
-
-void *plat_marvell_get_skip_image_data(void)
-{
- /* Return the skip_image configurations */
- return &skip_im;
-}
-#endif
-#endif
diff --git a/plat/marvell/a8k/a80x0/board/phy-porting-layer.h b/plat/marvell/a8k/a80x0/board/phy-porting-layer.h
deleted file mode 100644
index abd85b5d25..0000000000
--- a/plat/marvell/a8k/a80x0/board/phy-porting-layer.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * Copyright (C) 2018 Marvell International Ltd.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- * https://spdx.org/licenses
- */
-
-#ifndef PHY_PORTING_LAYER_H
-#define PHY_PORTING_LAYER_H
-
-#define MAX_LANE_NR 6
-
-static const struct xfi_params
- xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
- /* AP0 */
- {
- /* CP 0 */
- {
- { 0 }, /* Comphy0 */
- { 0 }, /* Comphy1 */
- { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
- .align90 = 0x5f,
- .g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
- .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
- .g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
- .g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
- .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
- .valid = 0x1 }, /* Comphy2 */
- { 0 }, /* Comphy3 */
- { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
- .align90 = 0x5f,
- .g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
- .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
- .g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
- .g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
- .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
- .valid = 0x1 }, /* Comphy4 */
- { 0 }, /* Comphy5 */
- },
-
- /* CP 1 */
- {
- { 0 }, /* Comphy0 */
- { 0 }, /* Comphy1 */
- { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
- .align90 = 0x5f,
- .g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
- .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
- .g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
- .g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
- .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
- .valid = 0x1 }, /* Comphy2 */
- { 0 }, /* Comphy3 */
- { .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf,
- .align90 = 0x5f,
- .g1_dfe_res = 0x2, .g1_amp = 0x1c, .g1_emph = 0xe,
- .g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1,
- .g1_tx_emph_en = 0x1, .g1_tx_emph = 0x0,
- .g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
- .g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
- .valid = 0x1 }, /* Comphy4 */
- { 0 }, /* Comphy5 */
- },
- },
-};
-
-static const struct sata_params
- sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
- /* AP0 */
- {
- /* CP 0 */
- {
- { 0 }, /* Comphy0 */
- { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
- .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
- .g1_emph_en = 0x1, .g2_emph_en = 0x1,
- .g3_emph_en = 0x1,
- .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
- .g3_tx_amp_adj = 0x1,
- .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
- .g3_tx_emph_en = 0x0,
- .g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
- .g3_tx_emph = 0x1,
- .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
- .g3_ffe_cap_sel = 0xf,
- .align90 = 0x61,
- .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
- .g3_rx_selmuff = 0x3,
- .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
- .g3_rx_selmufi = 0x3,
- .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
- .g3_rx_selmupf = 0x2,
- .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
- .g3_rx_selmupi = 0x2,
- .valid = 0x1
- }, /* Comphy1 */
- { 0 }, /* Comphy2 */
- { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
- .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
- .g1_emph_en = 0x1, .g2_emph_en = 0x1,
- .g3_emph_en = 0x1,
- .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
- .g3_tx_amp_adj = 0x1,
- .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
- .g3_tx_emph_en = 0x0,
- .g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
- .g3_tx_emph = 0x1,
- .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
- .g3_ffe_cap_sel = 0xf,
- .align90 = 0x61,
- .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
- .g3_rx_selmuff = 0x3,
- .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
- .g3_rx_selmufi = 0x3,
- .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
- .g3_rx_selmupf = 0x2,
- .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
- .g3_rx_selmupi = 0x2,
- .valid = 0x1
- }, /* Comphy3 */
- { 0 }, /* Comphy4 */
- { 0 }, /* Comphy5 */
- },
-
- /* CP 1 */
- {
- { 0 }, /* Comphy0 */
- { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
- .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
- .g1_emph_en = 0x1, .g2_emph_en = 0x1,
- .g3_emph_en = 0x1,
- .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
- .g3_tx_amp_adj = 0x1,
- .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
- .g3_tx_emph_en = 0x0,
- .g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
- .g3_tx_emph = 0x1,
- .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
- .g3_ffe_cap_sel = 0xf,
- .align90 = 0x61,
- .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
- .g3_rx_selmuff = 0x3,
- .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
- .g3_rx_selmufi = 0x3,
- .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
- .g3_rx_selmupf = 0x2,
- .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
- .g3_rx_selmupi = 0x2,
- .valid = 0x1
- }, /* Comphy1 */
- { 0 }, /* Comphy2 */
- { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
- .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
- .g1_emph_en = 0x1, .g2_emph_en = 0x1,
- .g3_emph_en = 0x1,
- .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1,
- .g3_tx_amp_adj = 0x1,
- .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0,
- .g3_tx_emph_en = 0x0,
- .g1_tx_emph = 0x1, .g2_tx_emph = 0x1,
- .g3_tx_emph = 0x1,
- .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4,
- .g3_ffe_cap_sel = 0xf,
- .align90 = 0x61,
- .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3,
- .g3_rx_selmuff = 0x3,
- .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0,
- .g3_rx_selmufi = 0x3,
- .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1,
- .g3_rx_selmupf = 0x2,
- .g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0,
- .g3_rx_selmupi = 0x2,
- .valid = 0x1
- }, /* Comphy3 */
- { 0 }, /* Comphy4 */
- { 0 }, /* Comphy5 */
-
- },
- },
-};
-#endif /* PHY_PORTING_LAYER_H */
diff --git a/plat/marvell/a8k/a80x0/mvebu_def.h b/plat/marvell/a8k/a80x0/mvebu_def.h
deleted file mode 100644
index 3fa119af62..0000000000
--- a/plat/marvell/a8k/a80x0/mvebu_def.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (C) 2018 Marvell International Ltd.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- * https://spdx.org/licenses
- */
-
-#ifndef MVEBU_DEF_H
-#define MVEBU_DEF_H
-
-#include <a8k_plat_def.h>
-
-#define CP_COUNT 2 /* A80x0 has both CP0 & CP1 */
-#define I2C_SPD_ADDR 0x53 /* Access SPD data */
-#define I2C_SPD_P0_ADDR 0x36 /* Select SPD data page 0 */
-
-#endif /* MVEBU_DEF_H */
diff --git a/plat/marvell/a8k/a80x0/platform.mk b/plat/marvell/a8k/a80x0/platform.mk
deleted file mode 100644
index 00d24b2789..0000000000
--- a/plat/marvell/a8k/a80x0/platform.mk
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# Copyright (C) 2018 Marvell International Ltd.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-# https://spdx.org/licenses
-#
-
-PCI_EP_SUPPORT := 0
-
-CP_NUM := 2
-$(eval $(call add_define,CP_NUM))
-
-DOIMAGE_SEC := tools/doimage/secure/sec_img_8K.cfg
-
-MARVELL_MOCHI_DRV := drivers/marvell/mochi/apn806_setup.c
-
-include plat/marvell/a8k/common/a8k_common.mk
-
-include plat/marvell/common/marvell_common.mk
-PLAT_INCLUDES += -Iplat/marvell/a8k/a80x0/board