diff options
author | Victor Chong <victor.chong@linaro.org> | 2018-02-01 00:35:22 +0900 |
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committer | Victor Chong <victor.chong@linaro.org> | 2018-02-08 02:14:46 +0900 |
commit | 0d8052a4eacc73aa808bf4b242f9f64b62875b9d (patch) | |
tree | cd7db91dac6aae05061f5a386214c41d34dd1e7c /plat/hisilicon/poplar/bl2_plat_setup.c | |
parent | 8ad132b3f176d0552b28f1fe77f8d1321449b4ef (diff) | |
download | trusted-firmware-a-0d8052a4eacc73aa808bf4b242f9f64b62875b9d.tar.gz |
poplar: Add LOAD_IMAGE_V2 support
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'plat/hisilicon/poplar/bl2_plat_setup.c')
-rw-r--r-- | plat/hisilicon/poplar/bl2_plat_setup.c | 173 |
1 files changed, 149 insertions, 24 deletions
diff --git a/plat/hisilicon/poplar/bl2_plat_setup.c b/plat/hisilicon/poplar/bl2_plat_setup.c index 7edfab7ff4..a338396fa2 100644 --- a/plat/hisilicon/poplar/bl2_plat_setup.c +++ b/plat/hisilicon/poplar/bl2_plat_setup.c @@ -9,6 +9,7 @@ #include <bl_common.h> #include <console.h> #include <debug.h> +#include <desc_image_load.h> #include <dw_mmc.h> #include <emmc.h> #include <errno.h> @@ -28,6 +29,15 @@ #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); + +#if !LOAD_IMAGE_V2 + +/******************************************************************************* + * This structure represents the superset of information that is passed to + * BL31, e.g. while passing control to it from BL2, bl31_params + * and other platform specific params + ******************************************************************************/ typedef struct bl2_to_bl31_params_mem { bl31_params_t bl31_params; image_info_t bl31_image_info; @@ -38,7 +48,6 @@ typedef struct bl2_to_bl31_params_mem { entry_point_info_t bl31_ep_info; } bl2_to_bl31_params_mem_t; -static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); static bl2_to_bl31_params_mem_t bl31_params_mem; meminfo_t *bl2_plat_sec_mem_layout(void) @@ -46,6 +55,134 @@ meminfo_t *bl2_plat_sec_mem_layout(void) return &bl2_tzram_layout; } +#ifdef SCP_BL2_BASE +void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) +{ + /* + * This platform has no SCP_BL2 yet + */ +} +#endif +#endif /* LOAD_IMAGE_V2 */ + +/******************************************************************************* + * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. + * Return 0 on success, -1 otherwise. + ******************************************************************************/ +#if LOAD_IMAGE_V2 +int plat_poplar_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info) +#else +int bl2_plat_handle_scp_bl2(struct image_info *scp_bl2_image_info) +#endif +{ + /* + * This platform has no SCP_BL2 yet + */ + return 0; +} + +/******************************************************************************* + * Gets SPSR for BL32 entry + ******************************************************************************/ +uint32_t poplar_get_spsr_for_bl32_entry(void) +{ + /* + * The Secure Payload Dispatcher service is responsible for + * setting the SPSR prior to entry into the BL3-2 image. + */ + return 0; +} + +/******************************************************************************* + * Gets SPSR for BL33 entry + ******************************************************************************/ +#ifndef AARCH32 +uint32_t poplar_get_spsr_for_bl33_entry(void) +{ + unsigned long el_status; + unsigned int mode; + uint32_t spsr; + + /* Figure out what mode we enter the non-secure world in */ + el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; + el_status &= ID_AA64PFR0_ELX_MASK; + + mode = (el_status) ? MODE_EL2 : MODE_EL1; + + /* + * TODO: Consider the possibility of specifying the SPSR in + * the FIP ToC and allowing the platform to have a say as + * well. + */ + spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + return spsr; +} +#else +uint32_t poplar_get_spsr_for_bl33_entry(void) +{ + unsigned int hyp_status, mode, spsr; + + hyp_status = GET_VIRT_EXT(read_id_pfr1()); + + mode = (hyp_status) ? MODE32_hyp : MODE32_svc; + + /* + * TODO: Consider the possibility of specifying the SPSR in + * the FIP ToC and allowing the platform to have a say as + * well. + */ + spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, + SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); + return spsr; +} +#endif /* AARCH32 */ + +#if LOAD_IMAGE_V2 +int poplar_bl2_handle_post_image_load(unsigned int image_id) +{ + int err = 0; + bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); + + assert(bl_mem_params); + + switch (image_id) { +#ifdef AARCH64 + case BL32_IMAGE_ID: + bl_mem_params->ep_info.spsr = poplar_get_spsr_for_bl32_entry(); + break; +#endif + + case BL33_IMAGE_ID: + /* BL33 expects to receive the primary CPU MPID (through r0) */ + bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); + bl_mem_params->ep_info.spsr = poplar_get_spsr_for_bl33_entry(); + break; + +#ifdef SCP_BL2_BASE + case SCP_BL2_IMAGE_ID: + /* The subsequent handling of SCP_BL2 is platform specific */ + err = plat_poplar_bl2_handle_scp_bl2(&bl_mem_params->image_info); + if (err) { + WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); + } + break; +#endif + } + + return err; +} + +/******************************************************************************* + * This function can be used by the platforms to update/use image + * information for given `image_id`. + ******************************************************************************/ +int bl2_plat_handle_post_image_load(unsigned int image_id) +{ + return poplar_bl2_handle_post_image_load(image_id); +} + +#else /* LOAD_IMAGE_V2 */ + bl31_params_t *bl2_plat_get_bl31_params(void) { bl31_params_t *bl2_to_bl31_params = NULL; @@ -92,6 +229,10 @@ bl31_params_t *bl2_plat_get_bl31_params(void) struct entry_point_info *bl2_plat_get_bl31_ep_info(void) { +#if DEBUG + bl31_params_mem.bl31_ep_info.args.arg1 = POPLAR_BL31_PLAT_PARAM_VAL; +#endif + return &bl31_params_mem.bl31_ep_info; } @@ -138,32 +279,11 @@ void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) } #endif /* BL32_BASE */ -static uint32_t hisi_get_spsr_for_bl33_entry(void) -{ - unsigned long el_status; - unsigned int mode; - uint32_t spsr; - - /* Figure out what mode we enter the non-secure world in */ - el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; - el_status &= ID_AA64PFR0_ELX_MASK; - - mode = (el_status) ? MODE_EL2 : MODE_EL1; - - /* - * TODO: Consider the possibility of specifying the SPSR in - * the FIP ToC and allowing the platform to have a say as - * well. - */ - spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); - return spsr; -} - void bl2_plat_set_bl33_ep_info(image_info_t *image, entry_point_info_t *bl33_ep_info) { SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); - bl33_ep_info->spsr = hisi_get_spsr_for_bl33_entry(); + bl33_ep_info->spsr = poplar_get_spsr_for_bl33_entry(); bl33_ep_info->args.arg2 = image->image_size; } @@ -180,6 +300,7 @@ void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) bl33_meminfo->free_base = DDR_BASE; bl33_meminfo->free_size = DDR_SIZE; } +#endif /* LOAD_IMAGE_V2 */ void bl2_early_platform_setup(meminfo_t *mem_layout) { @@ -217,7 +338,11 @@ void bl2_platform_setup(void) { } -unsigned long plat_get_ns_image_entrypoint(void) +uintptr_t plat_get_ns_image_entrypoint(void) { +#ifdef PRELOADED_BL33_BASE + return PRELOADED_BL33_BASE; +#else return PLAT_POPLAR_NS_IMAGE_OFFSET; +#endif } |