aboutsummaryrefslogtreecommitdiff
path: root/plat/hisilicon/hikey960/include/platform_def.h
diff options
context:
space:
mode:
authordavidcunado-arm <david.cunado@arm.com>2018-03-08 10:39:52 +0000
committerGitHub <noreply@github.com>2018-03-08 10:39:52 +0000
commitbf35944bf64480f72b3832dbeddf215e67941660 (patch)
treea5beb8aa702b4795d237a5591ba7f0a47ab82572 /plat/hisilicon/hikey960/include/platform_def.h
parentf5c1eed22c885482eda40153d8ce894afb5131ad (diff)
parent4e858ba0edaf69d3adf6fd1382299905fcb7c7fe (diff)
downloadtrusted-firmware-a-bf35944bf64480f72b3832dbeddf215e67941660.tar.gz
Merge pull request #1277 from hzhuang1/testing/bl2_el3_v0.6
hikey: migrate to BL2_EL3
Diffstat (limited to 'plat/hisilicon/hikey960/include/platform_def.h')
-rw-r--r--plat/hisilicon/hikey960/include/platform_def.h12
1 files changed, 3 insertions, 9 deletions
diff --git a/plat/hisilicon/hikey960/include/platform_def.h b/plat/hisilicon/hikey960/include/platform_def.h
index 36fd3b5317..beff47c0e4 100644
--- a/plat/hisilicon/hikey960/include/platform_def.h
+++ b/plat/hisilicon/hikey960/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -56,8 +56,8 @@
/*
* BL2 specific defines.
*/
-#define BL2_BASE (BL1_RW_BASE + 0x8000) /* 1AC1_8000 */
-#define BL2_LIMIT (BL2_BASE + 0x40000) /* 1AC5_8000 */
+#define BL2_BASE (0x1AC00000)
+#define BL2_LIMIT (BL2_BASE + 0x58000) /* 1AC5_8000 */
/*
* BL31 specific defines.
@@ -75,13 +75,11 @@
#define BL32_DRAM_BASE DDR_SEC_BASE
#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
-#if LOAD_IMAGE_V2
#ifdef SPD_opteed
/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
#define HIKEY960_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
#define HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
#endif
-#endif
#if (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_DRAM_ID)
#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
@@ -121,15 +119,11 @@
#endif
#ifdef IMAGE_BL2
-#if LOAD_IMAGE_V2
#ifdef SPD_opteed
#define MAX_XLAT_TABLES 4
#else
#define MAX_XLAT_TABLES 3
#endif
-#else
-#define MAX_XLAT_TABLES 3
-#endif
#endif
#define MAX_MMAP_REGIONS 16