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authorAndre Przywara <andre.przywara@arm.com>2018-09-20 21:13:55 +0100
committerAndre Przywara <andre.przywara@arm.com>2018-10-20 16:23:59 +0100
commitc3af6b0052b343943b8ed4e51658343c966bfc7a (patch)
tree1db5412743dd2b9b89fbb7b67a4df4b517fbf561 /plat/allwinner/common/include
parenta80490c53e6eb77c21156cca5670599f13366d61 (diff)
downloadtrusted-firmware-a-c3af6b0052b343943b8ed4e51658343c966bfc7a.tar.gz
allwinner: Adjust memory mapping to fit into 256MB
At the moment we map as much of the DRAM into EL3 as possible, however we actually don't use it. The only exception is the secure DRAM for BL32 (if that is configured). To decrease the memory footprint of ATF, we save on some page tables by reducing the memory mapping to the actually required regions: SRAM, device MMIO, secure DRAM and U-Boot (to be used later). This introduces a non-identity mapping for the DRAM regions. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'plat/allwinner/common/include')
-rw-r--r--plat/allwinner/common/include/platform_def.h12
1 files changed, 9 insertions, 3 deletions
diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h
index b46d410165..b7cf30f5a3 100644
--- a/plat/allwinner/common/include/platform_def.h
+++ b/plat/allwinner/common/include/platform_def.h
@@ -18,11 +18,17 @@
/* The traditional U-Boot load address is 160MB into DRAM, so at 0x4a000000 */
#define PLAT_SUNXI_NS_IMAGE_OFFSET (SUNXI_DRAM_BASE + (160U << 20))
+/* How much memory to reserve as secure for BL32, if configured */
+#define SUNXI_DRAM_SEC_SIZE (32U << 20)
+
+/* How much DRAM to map */
+#define SUNXI_DRAM_MAP_SIZE (64U << 20)
+
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
#define MAX_MMAP_REGIONS (4 + PLATFORM_MMAP_REGIONS)
-#define MAX_XLAT_TABLES 2
+#define MAX_XLAT_TABLES 1
#define PLAT_MAX_PWR_LVL_STATES U(2)
#define PLAT_MAX_RET_STATE U(1)
@@ -34,13 +40,13 @@
PLATFORM_CORE_COUNT)
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28)
#define PLATFORM_CLUSTER_COUNT 1
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
PLATFORM_MAX_CPUS_PER_CLUSTER)
#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
-#define PLATFORM_MMAP_REGIONS 3
+#define PLATFORM_MMAP_REGIONS 4
#define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT)
#ifndef SPD_none