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author | Bipin Ravi <bipin.ravi@arm.com> | 2022-06-08 15:27:00 -0500 |
---|---|---|
committer | Bipin Ravi <bipin.ravi@arm.com> | 2022-06-16 12:23:53 -0500 |
commit | 7bf1a7aaaa41034587e43d5805b42da83090b85b (patch) | |
tree | bc1247da9e5ebc9afd38134a264673fbe01f1d73 /lib | |
parent | 65a5e1c04df56dbc0feb270fbae13c884020a5b9 (diff) | |
download | trusted-firmware-a-7bf1a7aaaa41034587e43d5805b42da83090b85b.tar.gz |
fix(errata): workaround for Cortex-A77 erratum 2356587
Cortex-A77 erratum 2356587 is a cat B erratum that applies to revisions
r0p0 - r1p1 and is still open. The workaround is to set bit[0] of
CPUACTLR2_EL1 to force PLDW/PFRM ST to behave like PLD/PRFM LD and not
cause invalidations to other PE caches.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1152370/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I243cfd587bca06ffd2a7be5bce28f8d2c5e68230
Diffstat (limited to 'lib')
-rw-r--r-- | lib/cpus/aarch64/cortex_a77.S | 34 | ||||
-rw-r--r-- | lib/cpus/cpu-ops.mk | 8 |
2 files changed, 42 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S index e7365e28c1..aa66e94ea5 100644 --- a/lib/cpus/aarch64/cortex_a77.S +++ b/lib/cpus/aarch64/cortex_a77.S @@ -199,6 +199,34 @@ func check_errata_1791578 b cpu_rev_var_ls endfunc check_errata_1791578 + /* -------------------------------------------------- + * Errata Workaround for Cortex A77 Errata #2356587. + * This applies to revisions r0p0, r1p0, and r1p1 and is still open. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a77_2356587_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_2356587 + cbz x0, 1f + + /* Set bit 0 in ACTLR2_EL1 */ + mrs x1, CORTEX_A77_ACTLR2_EL1 + orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_0 + msr CORTEX_A77_ACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_a77_2356587_wa + +func check_errata_2356587 + /* Applies to r0p0, r1p0, and r1p1 right now */ + mov x1, #0x11 + b cpu_rev_var_ls +endfunc check_errata_2356587 + func check_errata_cve_2022_23960 #if WORKAROUND_CVE_2022_23960 mov x0, #ERRATA_APPLIES @@ -238,6 +266,11 @@ func cortex_a77_reset_func bl errata_a77_1791578_wa #endif +#if ERRATA_A77_2356587 + mov x0, x18 + bl errata_a77_2356587_wa +#endif + #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 /* * The Cortex-A77 generic vectors are overridden to apply errata @@ -285,6 +318,7 @@ func cortex_a77_errata_report report_errata ERRATA_A77_1925769, cortex_a77, 1925769 report_errata ERRATA_A77_1946167, cortex_a77, 1946167 report_errata ERRATA_A77_1791578, cortex_a77, 1791578 + report_errata ERRATA_A77_2356587, cortex_a77, 2356587 report_errata WORKAROUND_CVE_2022_23960, cortex_a77, cve_2022_23960 ldp x8, x30, [sp], #16 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index e14bb24f55..7d0d93d3fc 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -303,6 +303,10 @@ ERRATA_A77_1946167 ?=0 # to revisions r0p0, r1p0, and r1p1, it is still open. ERRATA_A77_1791578 ?=0 +# Flag to apply erratum 2356587 workaround during reset. This erratum applies +# to revisions r0p0, r1p0, and r1p1, it is still open. +ERRATA_A77_2356587 ?=0 + # Flag to apply erratum 1688305 workaround during reset. This erratum applies # to revisions r0p0 - r1p0 of the A78 cpu. ERRATA_A78_1688305 ?=0 @@ -843,6 +847,10 @@ $(eval $(call add_define,ERRATA_A77_1946167)) $(eval $(call assert_boolean,ERRATA_A77_1791578)) $(eval $(call add_define,ERRATA_A77_1791578)) +# Process ERRATA_A77_2356587 flag +$(eval $(call assert_boolean,ERRATA_A77_2356587)) +$(eval $(call add_define,ERRATA_A77_2356587)) + # Process ERRATA_A78_1688305 flag $(eval $(call assert_boolean,ERRATA_A78_1688305)) $(eval $(call add_define,ERRATA_A78_1688305)) |