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authorSoby Mathew <soby.mathew@arm.com>2018-12-12 09:43:49 +0000
committerGitHub <noreply@github.com>2018-12-12 09:43:49 +0000
commit4f7812e7ac2b363d76681e57c3eb055a67815f20 (patch)
treebd812498261de59b4e790221fc20be57074cabf2 /lib
parentfca0a51ff5a710c10f4512f07d88b2e828774a3a (diff)
parent48e1d350a0021a9a2f7e34041f28273dee9eb885 (diff)
downloadtrusted-firmware-a-4f7812e7ac2b363d76681e57c3eb055a67815f20.tar.gz
Merge pull request #1712 from jeenu-arm/ssbs
AArch64: Use SSBS for CVE_2018_3639 mitigation
Diffstat (limited to 'lib')
-rw-r--r--lib/cpus/aarch64/cortex_a76.S13
1 files changed, 11 insertions, 2 deletions
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index 1697c55dc8..4def143737 100644
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S
@@ -208,14 +208,20 @@ endfunc cortex_a76_disable_wa_cve_2018_3639
func cortex_a76_reset_func
mov x19, x30
+
#if WORKAROUND_CVE_2018_3639
+ /* If the PE implements SSBS, we don't need the dynamic workaround */
+ mrs x0, id_aa64pfr1_el1
+ lsr x0, x0, #ID_AA64PFR1_EL1_SSBS_SHIFT
+ and x0, x0, #ID_AA64PFR1_EL1_SSBS_MASK
+ cbnz x0, 1f
+
mrs x0, CORTEX_A76_CPUACTLR2_EL1
orr x0, x0, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
msr CORTEX_A76_CPUACTLR2_EL1, x0
isb
-#endif
-#if IMAGE_BL31 && WORKAROUND_CVE_2018_3639
+#ifdef IMAGE_BL31
/*
* The Cortex-A76 generic vectors are overwritten to use the vectors
* defined above. This is required in order to apply mitigation
@@ -226,6 +232,9 @@ func cortex_a76_reset_func
isb
#endif
+1:
+#endif
+
#if ERRATA_DSU_936184
bl errata_dsu_936184_wa
#endif