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authorDimitris Papastamos <dimitris.papastamos@arm.com>2017-06-20 09:25:10 +0100
committerDimitris Papastamos <dimitris.papastamos@arm.com>2017-06-22 16:42:23 +0100
commit6f512a3dfd61662dbdae4912fb6a320ae4d754d5 (patch)
treec82ac1f98b720f0a1f9239be24510e6ba592b14c /lib/xlat_tables
parente036660aabe4c49ef34fb154b00ecace9b91322e (diff)
downloadtrusted-firmware-a-6f512a3dfd61662dbdae4912fb6a320ae4d754d5.tar.gz
aarch32: Apply workaround for errata 813419 of Cortex-A57
TLBI instructions for monitor mode won't have the desired effect under specific circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and TLBI twice each time. Even though this errata is only needed in r0p0, the current errata framework is not prepared to apply run-time workarounds. The current one is always applied if compiled in, regardless of the CPU or its revision. The `DSB` instruction used when initializing the translation tables has been changed to `DSB ISH` as an optimization and to be consistent with the barriers used for the workaround. NOTE: This workaround is present in AArch64 TF and already enabled by default on Juno. Change-Id: I10b0baa304ed64b13b7b26ea766e61461e759dfa Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Diffstat (limited to 'lib/xlat_tables')
-rw-r--r--lib/xlat_tables/aarch32/xlat_tables.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/xlat_tables/aarch32/xlat_tables.c b/lib/xlat_tables/aarch32/xlat_tables.c
index 3c9051c345..9c1562407b 100644
--- a/lib/xlat_tables/aarch32/xlat_tables.c
+++ b/lib/xlat_tables/aarch32/xlat_tables.c
@@ -149,7 +149,7 @@ void enable_mmu_secure(unsigned int flags)
* and translation register writes are committed
* before enabling the MMU
*/
- dsb();
+ dsbish();
isb();
sctlr = read_sctlr();