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authorSummer Qin <summer.qin@arm.com>2017-03-16 17:16:34 +0000
committerSummer Qin <summer.qin@arm.com>2017-03-28 10:32:17 +0100
commit5d21b037e16ab8f7c5e63db84a6a9148b7a44a14 (patch)
treeeb7140f2cb1c602ee3d3dae70946d9e3ee82655c /lib/xlat_tables
parent891685a51146c50234bd5ce49d29cb0fd9f290c8 (diff)
downloadtrusted-firmware-a-5d21b037e16ab8f7c5e63db84a6a9148b7a44a14.tar.gz
Add support to change xlat_tables to non-cacheable
This patch adds an additional flag `XLAT_TABLE_NC` which marks the translation tables as Non-cacheable for MMU accesses. Change-Id: I7c28ab87f0ce67da237fadc3627beb6792860fd4 Signed-off-by: Summer Qin <summer.qin@arm.com>
Diffstat (limited to 'lib/xlat_tables')
-rw-r--r--lib/xlat_tables/aarch32/xlat_tables.c20
-rw-r--r--lib/xlat_tables/aarch64/xlat_tables.c17
2 files changed, 26 insertions, 11 deletions
diff --git a/lib/xlat_tables/aarch32/xlat_tables.c b/lib/xlat_tables/aarch32/xlat_tables.c
index e8408da89c..316a60e70e 100644
--- a/lib/xlat_tables/aarch32/xlat_tables.c
+++ b/lib/xlat_tables/aarch32/xlat_tables.c
@@ -130,13 +130,21 @@ void enable_mmu_secure(unsigned int flags)
tlbiall();
/*
- * Set TTBCR bits as well. Set TTBR0 table properties as Inner
- * & outer WBWA & shareable. Disable TTBR1.
+ * Set TTBCR bits as well. Set TTBR0 table properties. Disable TTBR1.
*/
- ttbcr = TTBCR_EAE_BIT |
- TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA |
- TTBCR_RGN0_INNER_WBA |
- (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE));
+ if (flags & XLAT_TABLE_NC) {
+ /* Inner & outer non-cacheable non-shareable. */
+ ttbcr = TTBCR_EAE_BIT |
+ TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC |
+ TTBCR_RGN0_INNER_NC |
+ (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE));
+ } else {
+ /* Inner & outer WBWA & shareable. */
+ ttbcr = TTBCR_EAE_BIT |
+ TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA |
+ TTBCR_RGN0_INNER_WBA |
+ (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE));
+ }
ttbcr |= TTBCR_EPD1_BIT;
write_ttbcr(ttbcr);
diff --git a/lib/xlat_tables/aarch64/xlat_tables.c b/lib/xlat_tables/aarch64/xlat_tables.c
index af12b9f196..ecb120220c 100644
--- a/lib/xlat_tables/aarch64/xlat_tables.c
+++ b/lib/xlat_tables/aarch64/xlat_tables.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -192,11 +192,18 @@ void init_xlat_tables(void)
_tlbi_fct(); \
\
/* Set TCR bits as well. */ \
- /* Inner & outer WBWA & shareable. */ \
/* Set T0SZ to (64 - width of virtual address space) */ \
- tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | \
- TCR_RGN_INNER_WBA | \
- (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
+ if (flags & XLAT_TABLE_NC) { \
+ /* Inner & outer non-cacheable non-shareable. */\
+ tcr = TCR_SH_NON_SHAREABLE | \
+ TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC | \
+ (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
+ } else { \
+ /* Inner & outer WBWA & shareable. */ \
+ tcr = TCR_SH_INNER_SHAREABLE | \
+ TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA | \
+ (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
+ } \
tcr |= _tcr_extra; \
write_tcr_el##_el(tcr); \
\