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authorSoby Mathew <soby.mathew@arm.com>2019-09-27 10:55:15 +0000
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2019-09-27 10:55:15 +0000
commitc5235cae8e0c7c70ae9b4a8c41d77db17c885418 (patch)
treee692795235ae210a47a0cdab5b968fb7727f1631 /lib/el3_runtime
parentace23683beb81354d6edbc61c087ab8c384d0631 (diff)
parentc3e8b0be9bde36d220beea5d0452ecd04dcd94c6 (diff)
downloadtrusted-firmware-a-c5235cae8e0c7c70ae9b4a8c41d77db17c885418.tar.gz
Merge "AArch32: Disable Secure Cycle Counter" into integration
Diffstat (limited to 'lib/el3_runtime')
-rw-r--r--lib/el3_runtime/aarch32/context_mgmt.c26
1 files changed, 22 insertions, 4 deletions
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index a4702fcc60..73d1e354d5 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -281,10 +281,28 @@ void cm_prepare_el3_exit(uint32_t security_state)
*
* HDCR.HPMN: Set to value of PMCR.N which is the
* architecturally-defined reset value.
+ *
+ * HDCR.HLP: Set to one so that event counter
+ * overflow, that is recorded in PMOVSCLR[0-30],
+ * occurs on the increment that changes
+ * PMEVCNTR<n>[63] from 1 to 0, when ARMv8.5-PMU is
+ * implemented. This bit is RES0 in versions of the
+ * architecture earlier than ARMv8.5, setting it to 1
+ * doesn't have any effect on them.
+ * This bit is Reserved, UNK/SBZP in ARMv7.
+ *
+ * HDCR.HPME: Set to zero to disable EL2 Event
+ * counters.
*/
- write_hdcr(HDCR_RESET_VAL |
- ((read_pmcr() & PMCR_N_BITS) >> PMCR_N_SHIFT));
-
+#if (ARM_ARCH_MAJOR > 7)
+ write_hdcr((HDCR_RESET_VAL | HDCR_HLP_BIT |
+ ((read_pmcr() & PMCR_N_BITS) >>
+ PMCR_N_SHIFT)) & ~HDCR_HPME_BIT);
+#else
+ write_hdcr((HDCR_RESET_VAL |
+ ((read_pmcr() & PMCR_N_BITS) >>
+ PMCR_N_SHIFT)) & ~HDCR_HPME_BIT);
+#endif
/*
* Set HSTR to its architectural reset value so that
* access to system registers in the cproc=1111