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authorSoby Mathew <soby.mathew@arm.com>2019-06-10 09:40:25 +0000
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2019-06-10 09:40:25 +0000
commitcb60e71e835e66001605cd08e5172d2e2b730d1f (patch)
tree9fc249521b2fb62d987e4776ccba10c24ddb42d5 /lib/cpus
parentf5b904ea97520deb0ea50812e2eaedfe0e868a5d (diff)
parent48d6b2643462b43ed617ca3751121a5587881e44 (diff)
downloadtrusted-firmware-a-cb60e71e835e66001605cd08e5172d2e2b730d1f.tar.gz
Merge changes from topic "jts/ti_fix" into integration
* changes: ti: k3: common: Remove coherency workaround for AM65x ti: k3: common: Use coherent memory for shared data
Diffstat (limited to 'lib/cpus')
-rw-r--r--lib/cpus/aarch64/cortex_a53.S4
1 files changed, 0 insertions, 4 deletions
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S
index 6fd3c53fdd..b105de26b2 100644
--- a/lib/cpus/aarch64/cortex_a53.S
+++ b/lib/cpus/aarch64/cortex_a53.S
@@ -279,13 +279,11 @@ endfunc cortex_a53_reset_func
func cortex_a53_core_pwr_dwn
mov x18, x30
-#if !TI_AM65X_WORKAROUND
/* ---------------------------------------------
* Turn off caches.
* ---------------------------------------------
*/
bl cortex_a53_disable_dcache
-#endif
/* ---------------------------------------------
* Flush L1 caches.
@@ -305,13 +303,11 @@ endfunc cortex_a53_core_pwr_dwn
func cortex_a53_cluster_pwr_dwn
mov x18, x30
-#if !TI_AM65X_WORKAROUND
/* ---------------------------------------------
* Turn off caches.
* ---------------------------------------------
*/
bl cortex_a53_disable_dcache
-#endif
/* ---------------------------------------------
* Flush L1 caches.