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authorJohn Tsichritzis <john.tsichritzis@arm.com>2018-10-08 17:09:43 +0100
committerJohn Tsichritzis <john.tsichritzis@arm.com>2019-03-14 11:39:40 +0000
commita4546e80f523f9785be6ba8756afd1ec9eec40c7 (patch)
tree040c4ad9a98dd912c2f9f940132d36df0eda0b9a /lib/cpus
parent620d9832f96ffcaf86d38b703ca913438d6eea7c (diff)
downloadtrusted-firmware-a-a4546e80f523f9785be6ba8756afd1ec9eec40c7.tar.gz
Introduce preliminary support for Neoverse Zeus
Change-Id: If56d1e200a31bd716726d7fdc1cc0ae8a63ba3ee Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
Diffstat (limited to 'lib/cpus')
-rw-r--r--lib/cpus/aarch64/neoverse_zeus.S60
1 files changed, 60 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/neoverse_zeus.S b/lib/cpus/aarch64/neoverse_zeus.S
new file mode 100644
index 0000000000..79c8b2fdf4
--- /dev/null
+++ b/lib/cpus/aarch64/neoverse_zeus.S
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2019, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <neoverse_zeus.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+ /* ---------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ---------------------------------------------
+ */
+func neoverse_zeus_core_pwr_dwn
+ /* ---------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------
+ */
+ mrs x0, NEOVERSE_ZEUS_CPUPWRCTLR_EL1
+ orr x0, x0, #NEOVERSE_ZEUS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ msr NEOVERSE_ZEUS_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc neoverse_zeus_core_pwr_dwn
+
+ /*
+ * Errata printing function for Neoverse Zeus. Must follow AAPCS.
+ */
+#if REPORT_ERRATA
+func neoverse_zeus_errata_report
+ ret
+endfunc neoverse_zeus_errata_report
+#endif
+
+ /* ---------------------------------------------
+ * This function provides Neoverse-Zeus specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.neoverse_zeus_regs, "aS"
+neoverse_zeus_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func neoverse_zeus_cpu_reg_dump
+ adr x6, neoverse_zeus_regs
+ mrs x8, NEOVERSE_ZEUS_CPUECTLR_EL1
+ ret
+endfunc neoverse_zeus_cpu_reg_dump
+
+declare_cpu_ops neoverse_zeus, NEOVERSE_ZEUS_MIDR, \
+ CPU_NO_RESET_FUNC, \
+ neoverse_zeus_core_pwr_dwn