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author | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-04-18 14:34:11 +0100 |
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committer | Louis Mayencourt <louis.mayencourt@arm.com> | 2019-04-18 14:55:46 +0100 |
commit | 632ab3eb26fcef5561cc3d0314886fd9b2793c1f (patch) | |
tree | 805b16e71e3a7155ad8e55b0251c08d4e6cf1b16 /lib/cpus | |
parent | 0e985d708e8f429c1fa1f557d3eea90e32de5228 (diff) | |
download | trusted-firmware-a-632ab3eb26fcef5561cc3d0314886fd9b2793c1f.tar.gz |
Neoverse N1: Forces cacheable atomic to near
This patch forces all cacheable atomic instructions to be near, which
improves performance in highly contended parallelized use-cases.
Change-Id: I93fac62847f4af8d5eaaf3b52318c30893e947d3
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Diffstat (limited to 'lib/cpus')
-rw-r--r-- | lib/cpus/aarch64/neoverse_n1.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S index 060c625d41..ce63899a7e 100644 --- a/lib/cpus/aarch64/neoverse_n1.S +++ b/lib/cpus/aarch64/neoverse_n1.S @@ -50,6 +50,12 @@ func neoverse_n1_reset_func /* Disables speculative loads */ msr SSBS, xzr + /* Forces all cacheable atomic instructions to be near */ + mrs x0, NEOVERSE_N1_CPUACTLR2_EL1 + orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 + msr NEOVERSE_N1_CPUACTLR2_EL1, x0 + isb + bl cpu_get_rev_var mov x18, x0 |