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author | Soby Mathew <soby.mathew@arm.com> | 2019-05-07 14:31:25 +0000 |
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committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2019-05-07 14:31:25 +0000 |
commit | 0cdbd023e175cb4428801c28d640a80f2bda6bea (patch) | |
tree | 42f0579a52905bc47db656a04075a783277641af /lib/cpus | |
parent | 854ca7daf9bbf4762d698128bfe030e0cebea956 (diff) | |
parent | f85edcea5ff651a47fc1434d2d9b5475cc56aa29 (diff) | |
download | trusted-firmware-a-0cdbd023e175cb4428801c28d640a80f2bda6bea.tar.gz |
Merge changes from topic "sm/fix_a76_errata" into integration
* changes:
Workaround for cortex-A76 errata 1286807
Cortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112
Diffstat (limited to 'lib/cpus')
-rw-r--r-- | lib/cpus/aarch64/cortex_a76.S | 133 | ||||
-rw-r--r-- | lib/cpus/cpu-ops.mk | 40 |
2 files changed, 172 insertions, 1 deletions
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S index 6fe6afe3db..b48283cbb9 100644 --- a/lib/cpus/aarch64/cortex_a76.S +++ b/lib/cpus/aarch64/cortex_a76.S @@ -213,7 +213,7 @@ func errata_a76_1073348_wa isb 1: ret x17 - endfunc errata_a76_1073348_wa +endfunc errata_a76_1073348_wa func check_errata_1073348 mov x1, #0x10 @@ -276,6 +276,117 @@ func check_errata_1220197 b cpu_rev_var_ls endfunc check_errata_1220197 + /* -------------------------------------------------- + * Errata Workaround for Cortex A76 Errata #1257314. + * This applies only to revision <= r3p0 of Cortex A76. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a76_1257314_wa + /* + * Compare x0 against revision r3p0 + */ + mov x17, x30 + bl check_errata_1257314 + cbz x0, 1f + mrs x1, CORTEX_A76_CPUACTLR3_EL1 + orr x1, x1, CORTEX_A76_CPUACTLR3_EL1_BIT_10 + msr CORTEX_A76_CPUACTLR3_EL1, x1 + isb +1: + ret x17 +endfunc errata_a76_1257314_wa + +func check_errata_1257314 + mov x1, #0x30 + b cpu_rev_var_ls +endfunc check_errata_1257314 + + /* -------------------------------------------------- + * Errata Workaround for Cortex A76 Errata #1262888. + * This applies only to revision <= r3p0 of Cortex A76. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a76_1262888_wa + /* + * Compare x0 against revision r3p0 + */ + mov x17, x30 + bl check_errata_1262888 + cbz x0, 1f + mrs x1, CORTEX_A76_CPUECTLR_EL1 + orr x1, x1, CORTEX_A76_CPUECTLR_EL1_BIT_51 + msr CORTEX_A76_CPUECTLR_EL1, x1 + isb +1: + ret x17 +endfunc errata_a76_1262888_wa + +func check_errata_1262888 + mov x1, #0x30 + b cpu_rev_var_ls +endfunc check_errata_1262888 + + /* -------------------------------------------------- + * Errata Workaround for Cortex A76 Errata #1275112 + * and Errata #1262606. + * This applies only to revision <= r3p0 of Cortex A76. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a76_1275112_1262606_wa + /* + * Compare x0 against revision r3p0 + */ + mov x17, x30 + /* + * Since both errata #1275112 and #1262606 have the same check, we can + * invoke any one of them for the check here. + */ + bl check_errata_1275112 + cbz x0, 1f + mrs x1, CORTEX_A76_CPUACTLR_EL1 + orr x1, x1, CORTEX_A76_CPUACTLR_EL1_BIT_13 + msr CORTEX_A76_CPUACTLR_EL1, x1 + isb +1: + ret x17 +endfunc errata_a76_1275112_1262606_wa + +func check_errata_1262606 + mov x1, #0x30 + b cpu_rev_var_ls +endfunc check_errata_1262606 + +func check_errata_1275112 + mov x1, #0x30 + b cpu_rev_var_ls +endfunc check_errata_1275112 + + /* --------------------------------------------------- + * Errata Workaround for Cortex A76 Errata #1286807. + * This applies only to revision <= r3p0 of Cortex A76. + * Due to the nature of the errata it is applied unconditionally + * when built in, report it as applicable in this case + * --------------------------------------------------- + */ +func check_errata_1286807 +#if ERRATA_A76_1286807 + mov x0, #ERRATA_APPLIES + ret +#else + mov x1, #0x30 + b cpu_rev_var_ls +#endif +endfunc check_errata_1286807 + func check_errata_cve_2018_3639 #if WORKAROUND_CVE_2018_3639 mov x0, #ERRATA_APPLIES @@ -318,6 +429,21 @@ func cortex_a76_reset_func bl errata_a76_1220197_wa #endif +#if ERRATA_A76_1257314 + mov x0, x18 + bl errata_a76_1257314_wa +#endif + +#if ERRATA_A76_1262606 || ERRATA_A76_1275112 + mov x0, x18 + bl errata_a76_1275112_1262606_wa +#endif + +#if ERRATA_A76_1262888 + mov x0, x18 + bl errata_a76_1262888_wa +#endif + #if WORKAROUND_CVE_2018_3639 /* If the PE implements SSBS, we don't need the dynamic workaround */ mrs x0, id_aa64pfr1_el1 @@ -393,6 +519,11 @@ func cortex_a76_errata_report report_errata ERRATA_A76_1073348, cortex_a76, 1073348 report_errata ERRATA_A76_1130799, cortex_a76, 1130799 report_errata ERRATA_A76_1220197, cortex_a76, 1220197 + report_errata ERRATA_A76_1257314, cortex_a76, 1257314 + report_errata ERRATA_A76_1262606, cortex_a76, 1262606 + report_errata ERRATA_A76_1262888, cortex_a76, 1262888 + report_errata ERRATA_A76_1275112, cortex_a76, 1275112 + report_errata ERRATA_A76_1286807, cortex_a76, 1286807 report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639 report_errata ERRATA_DSU_798953, cortex_a76, dsu_798953 report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 4deb262d8f..e45d79d99a 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -210,6 +210,26 @@ ERRATA_A76_1130799 ?=0 # only to revision <= r2p0 of the Cortex A76 cpu. ERRATA_A76_1220197 ?=0 +# Flag to apply erratum 1257314 workaround during reset. This erratum applies +# only to revision <= r3p0 of the Cortex A76 cpu. +ERRATA_A76_1257314 ?=0 + +# Flag to apply erratum 1262606 workaround during reset. This erratum applies +# only to revision <= r3p0 of the Cortex A76 cpu. +ERRATA_A76_1262606 ?=0 + +# Flag to apply erratum 1262888 workaround during reset. This erratum applies +# only to revision <= r3p0 of the Cortex A76 cpu. +ERRATA_A76_1262888 ?=0 + +# Flag to apply erratum 1275112 workaround during reset. This erratum applies +# only to revision <= r3p0 of the Cortex A76 cpu. +ERRATA_A76_1275112 ?=0 + +# Flag to apply erratum 1286807 workaround during reset. This erratum applies +# only to revision <= r3p0 of the Cortex A76 cpu. +ERRATA_A76_1286807 ?=0 + # Flag to apply T32 CLREX workaround during reset. This erratum applies # only to r0p0 and r1p0 of the Neoverse N1 cpu. ERRATA_N1_1043202 ?=1 @@ -375,6 +395,26 @@ $(eval $(call add_define,ERRATA_A76_1130799)) $(eval $(call assert_boolean,ERRATA_A76_1220197)) $(eval $(call add_define,ERRATA_A76_1220197)) +# Process ERRATA_A76_1257314 flag +$(eval $(call assert_boolean,ERRATA_A76_1257314)) +$(eval $(call add_define,ERRATA_A76_1257314)) + +# Process ERRATA_A76_1262606 flag +$(eval $(call assert_boolean,ERRATA_A76_1262606)) +$(eval $(call add_define,ERRATA_A76_1262606)) + +# Process ERRATA_A76_1262888 flag +$(eval $(call assert_boolean,ERRATA_A76_1262888)) +$(eval $(call add_define,ERRATA_A76_1262888)) + +# Process ERRATA_A76_1275112 flag +$(eval $(call assert_boolean,ERRATA_A76_1275112)) +$(eval $(call add_define,ERRATA_A76_1275112)) + +# Process ERRATA_A76_1286807 flag +$(eval $(call assert_boolean,ERRATA_A76_1286807)) +$(eval $(call add_define,ERRATA_A76_1286807)) + # Process ERRATA_N1_1043202 flag $(eval $(call assert_boolean,ERRATA_N1_1043202)) $(eval $(call add_define,ERRATA_N1_1043202)) |