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authorSandrine Bailleux <sandrine.bailleux@arm.com>2016-03-01 14:01:03 +0000
committerSandrine Bailleux <sandrine.bailleux@arm.com>2016-03-03 16:55:25 +0000
commit5f654975bb20efa651e2567e234798cf5e8673f2 (patch)
tree4afbd31da5c3a77d752ad57fc0555be38555197a /lib/aarch64
parent9931932bfd3429aa8e98c33a26dfafcdbda71a43 (diff)
downloadtrusted-firmware-a-5f654975bb20efa651e2567e234798cf5e8673f2.tar.gz
Extend memory attributes to map non-cacheable memory
At the moment, the memory translation library allows to create memory mappings of 2 types: - Device nGnRE memory (named MT_DEVICE in the library); - Normal, Inner Write-back non-transient, Outer Write-back non-transient memory (named MT_MEMORY in the library). As a consequence, the library code treats the memory type field as a boolean: everything that is not device memory is normal memory and vice-versa. In reality, the ARMv8 architecture allows up to 8 types of memory to be used at a single time for a given exception level. This patch reworks the memory attributes such that the memory type is now defined as an integer ranging from 0 to 7 instead of a boolean. This makes it possible to extend the list of memory types supported by the memory translation library. The priority system dictating memory attributes for overlapping memory regions has been extended to cope with these changes but the algorithm at its core has been preserved. When a memory region is re-mapped with different memory attributes, the memory translation library examines the former attributes and updates them only if the new attributes create a more restrictive mapping. This behaviour is unchanged, only the manipulation of the value has been modified to cope with the new format. This patch also introduces a new type of memory mapping in the memory translation library: MT_NON_CACHEABLE, meaning Normal, Inner Non-cacheable, Outer Non-cacheable memory. This can be useful to map a non-cacheable memory region, such as a DMA buffer for example. The rules around the Execute-Never (XN) bit in a translation table for an MT_NON_CACHEABLE memory mapping have been aligned on the rules used for MT_MEMORY mappings: - If the memory is read-only then it is also executable (XN = 0); - If the memory is read-write then it is not executable (XN = 1). The shareability field for MT_NON_CACHEABLE mappings is always set as 'Outer-Shareable'. Note that this is not strictly needed since shareability is only relevant if the memory is a Normal Cacheable memory type, but this is to align with the existing device memory mappings setup. All Device and Normal Non-cacheable memory regions are always treated as Outer Shareable, regardless of the translation table shareability attributes. This patch also removes the 'ATTR_SO' and 'ATTR_SO_INDEX' #defines. They were introduced to map memory as Device nGnRnE (formerly called "Strongly-Ordered" memory in the ARMv7 architecture) but were not used anywhere in the code base. Removing them avoids any confusion about the memory types supported by the library. Upstream platforms do not currently use the MT_NON_CACHEABLE memory type. NOTE: THIS CHANGE IS SOURCE COMPATIBLE BUT PLATFORMS THAT RELY ON THE BINARY VALUES OF `mmap_attr_t` or the `attr` argument of `mmap_add_region()` MAY BE BROKEN. Change-Id: I717d6ed79b4c845a04e34132432f98b93d661d79
Diffstat (limited to 'lib/aarch64')
-rw-r--r--lib/aarch64/xlat_tables.c28
1 files changed, 26 insertions, 2 deletions
diff --git a/lib/aarch64/xlat_tables.c b/lib/aarch64/xlat_tables.c
index 2f2ca814eb..d28731f636 100644
--- a/lib/aarch64/xlat_tables.c
+++ b/lib/aarch64/xlat_tables.c
@@ -138,6 +138,7 @@ static unsigned long mmap_desc(unsigned attr, unsigned long addr_pa,
unsigned level)
{
unsigned long desc = addr_pa;
+ int mem_type;
desc |= level == 3 ? TABLE_DESC : BLOCK_DESC;
@@ -147,16 +148,23 @@ static unsigned long mmap_desc(unsigned attr, unsigned long addr_pa,
desc |= LOWER_ATTRS(ACCESS_FLAG);
- if (attr & MT_MEMORY) {
+ mem_type = MT_TYPE(attr);
+ if (mem_type == MT_MEMORY) {
desc |= LOWER_ATTRS(ATTR_IWBWA_OWBWA_NTR_INDEX | ISH);
if (attr & MT_RW)
desc |= UPPER_ATTRS(XN);
+ } else if (mem_type == MT_NON_CACHEABLE) {
+ desc |= LOWER_ATTRS(ATTR_NON_CACHEABLE_INDEX | OSH);
+ if (attr & MT_RW)
+ desc |= UPPER_ATTRS(XN);
} else {
+ assert(mem_type == MT_DEVICE);
desc |= LOWER_ATTRS(ATTR_DEVICE_INDEX | OSH);
desc |= UPPER_ATTRS(XN);
}
- debug_print(attr & MT_MEMORY ? "MEM" : "DEV");
+ debug_print((mem_type == MT_MEMORY) ? "MEM" :
+ ((mem_type == MT_NON_CACHEABLE) ? "NC" : "DEV"));
debug_print(attr & MT_RW ? "-RW" : "-RO");
debug_print(attr & MT_NS ? "-NS" : "-S");
@@ -167,6 +175,7 @@ static int mmap_region_attr(mmap_region_t *mm, unsigned long base_va,
unsigned long size)
{
int attr = mm->attr;
+ int old_mem_type, new_mem_type;
for (;;) {
++mm;
@@ -183,7 +192,20 @@ static int mmap_region_attr(mmap_region_t *mm, unsigned long base_va,
if ((mm->attr & attr) == attr)
continue; /* Region doesn't override attribs so skip */
+ /*
+ * Update memory mapping attributes in 2 steps:
+ * 1) Update access permissions and security state flags
+ * 2) Update memory type.
+ *
+ * See xlat_tables.h for details about the attributes priority
+ * system and the rules dictating whether attributes should be
+ * updated.
+ */
+ old_mem_type = MT_TYPE(attr);
+ new_mem_type = MT_TYPE(mm->attr);
attr &= mm->attr;
+ if (new_mem_type < old_mem_type)
+ attr = (attr & ~MT_TYPE_MASK) | new_mem_type;
if (mm->base_va > base_va ||
mm->base_va + mm->size < base_va + size)
@@ -309,6 +331,8 @@ void init_xlat_tables(void)
mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \
mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \
ATTR_IWBWA_OWBWA_NTR_INDEX); \
+ mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, \
+ ATTR_NON_CACHEABLE_INDEX); \
write_mair_el##_el(mair); \
\
/* Invalidate TLBs at the current exception level */ \