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author | Manish Pandey <manish.pandey2@arm.com> | 2020-06-26 13:59:38 +0000 |
---|---|---|
committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2020-06-26 13:59:38 +0000 |
commit | edd8188d32eb989c069da185f47425ac739bfdfd (patch) | |
tree | 6d3d5d39c2568592853a038d7903ee1419aba352 /include | |
parent | b8247e1189c0fe87e802773925fb3514afbd3bf2 (diff) | |
parent | 47d1773f90c84065c939ee190bb85f6221cd9dda (diff) | |
download | trusted-firmware-a-edd8188d32eb989c069da185f47425ac739bfdfd.tar.gz |
Merge changes Ib9c82b85,Ib348e097,I4dc315e4,I58a8ce44,Iebc03361, ... into integration
* changes:
plat: marvell: armada: a8k: add OP-TEE OS MMU tables
drivers: marvell: add support for mapping the entire LLC to SRAM
plat: marvell: armada: add LLC SRAM CCU setup for AP806/AP807 platforms
plat: marvell: armada: reduce memory size reserved for FIP image
plat: marvell: armada: platform definitions cleanup
plat: marvell: armada: a8k: check CCU window state before loading MSS BL2
drivers: marvell: add CCU driver API for window state checking
drivers: marvell: align and extend llc macros
plat: marvell: a8k: move address config of cp1/2 to BL2
plat: marvell: armada: re-enable BL32_BASE definition
plat: marvell: a8k: extend includes to take advantage of the phy_porting_layer
marvell: comphy: initialize common phy selector for AP mode
marvell: comphy: update rx_training procedure
plat: marvell: armada: configure amb for all CPs
plat: marvell: armada: modify PLAT_FAMILY name for 37xx SoCs
Diffstat (limited to 'include')
-rw-r--r-- | include/drivers/marvell/cache_llc.h | 36 | ||||
-rw-r--r-- | include/drivers/marvell/ccu.h | 1 | ||||
-rw-r--r-- | include/plat/marvell/armada/a3k/common/armada_common.h (renamed from include/plat/marvell/armada/a3700/common/armada_common.h) | 0 | ||||
-rw-r--r-- | include/plat/marvell/armada/a3k/common/board_marvell_def.h (renamed from include/plat/marvell/armada/a3700/common/board_marvell_def.h) | 2 | ||||
-rw-r--r-- | include/plat/marvell/armada/a3k/common/marvell_def.h (renamed from include/plat/marvell/armada/a3700/common/marvell_def.h) | 21 | ||||
-rw-r--r-- | include/plat/marvell/armada/a3k/common/plat_marvell.h (renamed from include/plat/marvell/armada/a3700/common/plat_marvell.h) | 0 | ||||
-rw-r--r-- | include/plat/marvell/armada/a8k/common/board_marvell_def.h | 3 | ||||
-rw-r--r-- | include/plat/marvell/armada/a8k/common/marvell_def.h | 55 |
8 files changed, 93 insertions, 25 deletions
diff --git a/include/drivers/marvell/cache_llc.h b/include/drivers/marvell/cache_llc.h index 85babb8d4b..b326474ee1 100644 --- a/include/drivers/marvell/cache_llc.h +++ b/include/drivers/marvell/cache_llc.h @@ -13,19 +13,35 @@ #define CACHE_LLC_H #define LLC_CTRL(ap) (MVEBU_LLC_BASE(ap) + 0x100) +#define LLC_SECURE_CTRL(ap) (MVEBU_LLC_BASE(ap) + 0x10C) #define LLC_SYNC(ap) (MVEBU_LLC_BASE(ap) + 0x700) -#define L2X0_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x77C) -#define L2X0_CLEAN_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7BC) -#define L2X0_CLEAN_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7FC) -#define LLC_TC0_LOCK(ap) (MVEBU_LLC_BASE(ap) + 0x920) +#define LLC_BANKED_MNT_AHR(ap) (MVEBU_LLC_BASE(ap) + 0x724) +#define LLC_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x77C) +#define LLC_BLK_ALOC(ap) (MVEBU_LLC_BASE(ap) + 0x78c) +#define LLC_CLEAN_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7BC) +#define LLC_CLEAN_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7FC) +#define LLC_TCN_LOCK(ap, tc) (MVEBU_LLC_BASE(ap) + 0x920 + 4 * (tc)) #define MASTER_LLC_CTRL LLC_CTRL(MVEBU_AP0) -#define MASTER_L2X0_INV_WAY L2X0_INV_WAY(MVEBU_AP0) -#define MASTER_LLC_TC0_LOCK LLC_TC0_LOCK(MVEBU_AP0) +#define MASTER_LLC_INV_WAY LLC_INV_WAY(MVEBU_AP0) +#define MASTER_LLC_TC0_LOCK LLC_TCN_LOCK(MVEBU_AP0, 0) #define LLC_CTRL_EN 1 #define LLC_EXCLUSIVE_EN 0x100 -#define LLC_WAY_MASK 0xFFFFFFFF +#define LLC_ALL_WAYS_MASK 0xFFFFFFFF + +/* AP806/AP807 - 1MB 8-ways LLC */ +#define LLC_WAYS 8 +#define LLC_WAY_MASK ((1 << LLC_WAYS) - 1) +#define LLC_SIZE (1024 * 1024) +#define LLC_WAY_SIZE (LLC_SIZE / LLC_WAYS) +#define LLC_TC_NUM 15 + +#define LLC_BLK_ALOC_WAY_ID(way) ((way) & 0x1f) +#define LLC_BLK_ALOC_WAY_DATA_DSBL (0x0 << 6) +#define LLC_BLK_ALOC_WAY_DATA_CLR (0x1 << 6) +#define LLC_BLK_ALOC_WAY_DATA_SET (0x3 << 6) +#define LLC_BLK_ALOC_BASE_ADDR(addr) ((addr) & (LLC_WAY_SIZE - 1)) #ifndef __ASSEMBLER__ void llc_cache_sync(int ap_index); @@ -36,6 +52,10 @@ void llc_disable(int ap_index); void llc_enable(int ap_index, int excl_mode); int llc_is_exclusive(int ap_index); void llc_runtime_enable(int ap_index); -#endif +#if LLC_SRAM +void llc_sram_enable(int ap_index); +void llc_sram_disable(int ap_index); +#endif /* LLC_SRAM */ +#endif /* __ASSEMBLY__ */ #endif /* CACHE_LLC_H */ diff --git a/include/drivers/marvell/ccu.h b/include/drivers/marvell/ccu.h index b0d1ec9840..413ffb972f 100644 --- a/include/drivers/marvell/ccu.h +++ b/include/drivers/marvell/ccu.h @@ -46,6 +46,7 @@ void ccu_dram_win_config(int ap_index, struct addr_map_win *win); void ccu_dram_target_set(int ap_index, uint32_t target); void ccu_save_win_all(int ap_id); void ccu_restore_win_all(int ap_id); +int ccu_is_win_enabled(int ap_index, uint32_t win_id); #endif #endif /* CCU_H */ diff --git a/include/plat/marvell/armada/a3700/common/armada_common.h b/include/plat/marvell/armada/a3k/common/armada_common.h index c6953fb713..c6953fb713 100644 --- a/include/plat/marvell/armada/a3700/common/armada_common.h +++ b/include/plat/marvell/armada/a3k/common/armada_common.h diff --git a/include/plat/marvell/armada/a3700/common/board_marvell_def.h b/include/plat/marvell/armada/a3k/common/board_marvell_def.h index 1782596629..bc3e04f001 100644 --- a/include/plat/marvell/armada/a3700/common/board_marvell_def.h +++ b/include/plat/marvell/armada/a3k/common/board_marvell_def.h @@ -71,6 +71,4 @@ #define MAX_IO_DEVICES 3 #define MAX_IO_HANDLES 4 -#define PLAT_MARVELL_TRUSTED_SRAM_SIZE 0x80000 /* 512 KB */ - #endif /* BOARD_MARVELL_DEF_H */ diff --git a/include/plat/marvell/armada/a3700/common/marvell_def.h b/include/plat/marvell/armada/a3k/common/marvell_def.h index eb13ba8afd..1394c05abb 100644 --- a/include/plat/marvell/armada/a3700/common/marvell_def.h +++ b/include/plat/marvell/armada/a3k/common/marvell_def.h @@ -49,15 +49,17 @@ */ #define MARVELL_LOCAL_STATE_OFF 2 +/* This leaves a gap between end of DRAM and start of ROM block */ +#define MARVELL_TRUSTED_DRAM_SIZE 0x80000 /* 512 KB */ + /* The first 4KB of Trusted SRAM are used as shared memory */ -#define MARVELL_TRUSTED_SRAM_BASE PLAT_MARVELL_ATF_BASE -#define MARVELL_SHARED_RAM_BASE MARVELL_TRUSTED_SRAM_BASE +#define MARVELL_SHARED_RAM_BASE PLAT_MARVELL_ATF_BASE #define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ /* The remaining Trusted SRAM is used to load the BL images */ #define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \ MARVELL_SHARED_RAM_SIZE) -#define MARVELL_BL_RAM_SIZE (PLAT_MARVELL_TRUSTED_SRAM_SIZE - \ +#define MARVELL_BL_RAM_SIZE (MARVELL_TRUSTED_DRAM_SIZE - \ MARVELL_SHARED_RAM_SIZE) #define MARVELL_DRAM_BASE ULL(0x0) @@ -65,7 +67,7 @@ #define MARVELL_DRAM_END (MARVELL_DRAM_BASE + \ MARVELL_DRAM_SIZE - 1) -#define MARVELL_IRQ_SEC_PHY_TIMER 29 +#define MARVELL_IRQ_SEC_PHY_TIMER 29 #define MARVELL_IRQ_SEC_SGI_0 8 #define MARVELL_IRQ_SEC_SGI_1 9 @@ -86,7 +88,6 @@ MARVELL_DRAM_SIZE, \ MT_MEMORY | MT_RW | MT_NS) - /* * The number of regions like RO(code), coherent and data required by * different BL stages which need to be mapped in the MMU. @@ -173,5 +174,15 @@ #define BL31_LIMIT (MARVELL_BL_RAM_BASE + \ MARVELL_BL_RAM_SIZE) +/***************************************************************************** + * BL32 specific defines. + ***************************************************************************** + */ +#define BL32_BASE PLAT_MARVELL_TRUSTED_RAM_BASE +#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_RAM_SIZE) + +#ifdef SPD_none +#undef BL32_BASE +#endif /* SPD_none */ #endif /* MARVELL_DEF_H */ diff --git a/include/plat/marvell/armada/a3700/common/plat_marvell.h b/include/plat/marvell/armada/a3k/common/plat_marvell.h index ea7cdcd4c3..ea7cdcd4c3 100644 --- a/include/plat/marvell/armada/a3700/common/plat_marvell.h +++ b/include/plat/marvell/armada/a3k/common/plat_marvell.h diff --git a/include/plat/marvell/armada/a8k/common/board_marvell_def.h b/include/plat/marvell/armada/a8k/common/board_marvell_def.h index 0da56e7afc..7e90f5f19c 100644 --- a/include/plat/marvell/armada/a8k/common/board_marvell_def.h +++ b/include/plat/marvell/armada/a8k/common/board_marvell_def.h @@ -71,7 +71,4 @@ #define MAX_IO_DEVICES 3 #define MAX_IO_HANDLES 4 -#define PLAT_MARVELL_TRUSTED_SRAM_SIZE 0x80000 /* 512 KB */ - - #endif /* BOARD_MARVELL_DEF_H */ diff --git a/include/plat/marvell/armada/a8k/common/marvell_def.h b/include/plat/marvell/armada/a8k/common/marvell_def.h index 4eda01f1e2..1245b88a20 100644 --- a/include/plat/marvell/armada/a8k/common/marvell_def.h +++ b/include/plat/marvell/armada/a8k/common/marvell_def.h @@ -47,15 +47,17 @@ */ #define MARVELL_LOCAL_STATE_OFF 2 +/* This leaves a gap between end of DRAM and start of ROM block */ +#define MARVELL_TRUSTED_DRAM_SIZE 0x80000 /* 512 KB */ + /* The first 4KB of Trusted SRAM are used as shared memory */ -#define MARVELL_TRUSTED_SRAM_BASE PLAT_MARVELL_ATF_BASE -#define MARVELL_SHARED_RAM_BASE MARVELL_TRUSTED_SRAM_BASE +#define MARVELL_SHARED_RAM_BASE PLAT_MARVELL_ATF_BASE #define MARVELL_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ /* The remaining Trusted SRAM is used to load the BL images */ #define MARVELL_BL_RAM_BASE (MARVELL_SHARED_RAM_BASE + \ MARVELL_SHARED_RAM_SIZE) -#define MARVELL_BL_RAM_SIZE (PLAT_MARVELL_TRUSTED_SRAM_SIZE - \ +#define MARVELL_BL_RAM_SIZE (MARVELL_TRUSTED_DRAM_SIZE - \ MARVELL_SHARED_RAM_SIZE) /* Non-shared DRAM */ #define MARVELL_DRAM_BASE ULL(0x0) @@ -75,9 +77,40 @@ #define MARVELL_IRQ_SEC_SGI_6 14 #define MARVELL_IRQ_SEC_SGI_7 15 -#define MARVELL_MAP_SHARED_RAM MAP_REGION_FLAT( \ - MARVELL_SHARED_RAM_BASE,\ - MARVELL_SHARED_RAM_SIZE,\ +#ifdef SPD_opteed +/* + * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to + * load/authenticate the trusted os extra image. The first 512KB of + * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading + * for OPTEE is paged image which only include the paging part using + * virtual memory but without "init" data. OPTEE will copy the "init" data + * (from pager image) to the first 512KB of TZC_DRAM, and then copy the + * extra image behind the "init" data. + */ +#define MARVELL_OPTEE_PAGEABLE_LOAD_BASE \ + (PLAT_MARVELL_TRUSTED_RAM_BASE + \ + PLAT_MARVELL_TRUSTED_RAM_SIZE - \ + MARVELL_OPTEE_PAGEABLE_LOAD_SIZE) +#define MARVELL_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 +#define MARVELL_OPTEE_PAGEABLE_LOAD_MEM \ + MAP_REGION_FLAT( \ + MARVELL_OPTEE_PAGEABLE_LOAD_BASE, \ + MARVELL_OPTEE_PAGEABLE_LOAD_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +/* + * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging + * support is enabled). + */ +#define MARVELL_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ + BL32_BASE, \ + BL32_LIMIT - BL32_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif /* SPD_opteed */ + +#define MARVELL_MAP_SECURE_RAM MAP_REGION_FLAT( \ + MARVELL_SHARED_RAM_BASE, \ + MARVELL_SHARED_RAM_SIZE, \ MT_MEMORY | MT_RW | MT_SECURE) #define MARVELL_MAP_DRAM MAP_REGION_FLAT( \ @@ -85,7 +118,6 @@ MARVELL_DRAM_SIZE, \ MT_MEMORY | MT_RW | MT_NS) - /* * The number of regions like RO(code), coherent and data required by * different BL stages which need to be mapped in the MMU. @@ -177,5 +209,14 @@ #define BL31_LIMIT (MARVELL_BL_RAM_BASE + \ MARVELL_BL_RAM_SIZE) +/******************************************************************************* + * BL32 specific defines. + ******************************************************************************/ +#define BL32_BASE PLAT_MARVELL_TRUSTED_RAM_BASE +#define BL32_LIMIT (BL32_BASE + PLAT_MARVELL_TRUSTED_RAM_SIZE) + +#ifdef SPD_none +#undef BL32_BASE +#endif /* SPD_none */ #endif /* MARVELL_DEF_H */ |