aboutsummaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorOlivier Deprez <olivier.deprez@arm.com>2021-04-07 21:25:26 +0200
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2021-04-07 21:25:26 +0200
commite729595fa908ae8c836002b8cc970ed84111fcd7 (patch)
treeb465eab10eac272619fd45598f0d1cd974b9edde /include
parentf0d84287b4daed35bc1871db43446ba5a12d780a (diff)
parenta7cf2743f3eb487912302aafc748c81bbd1fc603 (diff)
downloadtrusted-firmware-a-e729595fa908ae8c836002b8cc970ed84111fcd7.tar.gz
Merge "Fix: Remove save/restore of EL2 timer registers" into integration
Diffstat (limited to 'include')
-rw-r--r--include/lib/el3_runtime/aarch64/context.h126
1 files changed, 57 insertions, 69 deletions
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index 3135fb45b2..9d9f9d3325 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -160,86 +160,74 @@
#define CTX_AFSR1_EL2 U(0x10)
#define CTX_AMAIR_EL2 U(0x18)
#define CTX_CNTHCTL_EL2 U(0x20)
-#define CTX_CNTHP_CTL_EL2 U(0x28)
-#define CTX_CNTHP_CVAL_EL2 U(0x30)
-#define CTX_CNTHP_TVAL_EL2 U(0x38)
-#define CTX_CNTVOFF_EL2 U(0x40)
-#define CTX_CPTR_EL2 U(0x48)
-#define CTX_DBGVCR32_EL2 U(0x50)
-#define CTX_ELR_EL2 U(0x58)
-#define CTX_ESR_EL2 U(0x60)
-#define CTX_FAR_EL2 U(0x68)
-#define CTX_HACR_EL2 U(0x70)
-#define CTX_HCR_EL2 U(0x78)
-#define CTX_HPFAR_EL2 U(0x80)
-#define CTX_HSTR_EL2 U(0x88)
-#define CTX_ICC_SRE_EL2 U(0x90)
-#define CTX_ICH_HCR_EL2 U(0x98)
-#define CTX_ICH_VMCR_EL2 U(0xa0)
-#define CTX_MAIR_EL2 U(0xa8)
-#define CTX_MDCR_EL2 U(0xb0)
-#define CTX_PMSCR_EL2 U(0xb8)
-#define CTX_SCTLR_EL2 U(0xc0)
-#define CTX_SPSR_EL2 U(0xc8)
-#define CTX_SP_EL2 U(0xd0)
-#define CTX_TCR_EL2 U(0xd8)
-#define CTX_TPIDR_EL2 U(0xe0)
-#define CTX_TTBR0_EL2 U(0xe8)
-#define CTX_VBAR_EL2 U(0xf0)
-#define CTX_VMPIDR_EL2 U(0xf8)
-#define CTX_VPIDR_EL2 U(0x100)
-#define CTX_VTCR_EL2 U(0x108)
-#define CTX_VTTBR_EL2 U(0x110)
+#define CTX_CNTVOFF_EL2 U(0x28)
+#define CTX_CPTR_EL2 U(0x30)
+#define CTX_DBGVCR32_EL2 U(0x38)
+#define CTX_ELR_EL2 U(0x40)
+#define CTX_ESR_EL2 U(0x48)
+#define CTX_FAR_EL2 U(0x50)
+#define CTX_HACR_EL2 U(0x58)
+#define CTX_HCR_EL2 U(0x60)
+#define CTX_HPFAR_EL2 U(0x68)
+#define CTX_HSTR_EL2 U(0x70)
+#define CTX_ICC_SRE_EL2 U(0x78)
+#define CTX_ICH_HCR_EL2 U(0x80)
+#define CTX_ICH_VMCR_EL2 U(0x88)
+#define CTX_MAIR_EL2 U(0x90)
+#define CTX_MDCR_EL2 U(0x98)
+#define CTX_PMSCR_EL2 U(0xa0)
+#define CTX_SCTLR_EL2 U(0xa8)
+#define CTX_SPSR_EL2 U(0xb0)
+#define CTX_SP_EL2 U(0xb8)
+#define CTX_TCR_EL2 U(0xc0)
+#define CTX_TPIDR_EL2 U(0xc8)
+#define CTX_TTBR0_EL2 U(0xd0)
+#define CTX_VBAR_EL2 U(0xd8)
+#define CTX_VMPIDR_EL2 U(0xe0)
+#define CTX_VPIDR_EL2 U(0xe8)
+#define CTX_VTCR_EL2 U(0xf0)
+#define CTX_VTTBR_EL2 U(0xf8)
// Only if MTE registers in use
-#define CTX_TFSR_EL2 U(0x118)
+#define CTX_TFSR_EL2 U(0x100)
// Only if ENABLE_MPAM_FOR_LOWER_ELS==1
-#define CTX_MPAM2_EL2 U(0x120)
-#define CTX_MPAMHCR_EL2 U(0x128)
-#define CTX_MPAMVPM0_EL2 U(0x130)
-#define CTX_MPAMVPM1_EL2 U(0x138)
-#define CTX_MPAMVPM2_EL2 U(0x140)
-#define CTX_MPAMVPM3_EL2 U(0x148)
-#define CTX_MPAMVPM4_EL2 U(0x150)
-#define CTX_MPAMVPM5_EL2 U(0x158)
-#define CTX_MPAMVPM6_EL2 U(0x160)
-#define CTX_MPAMVPM7_EL2 U(0x168)
-#define CTX_MPAMVPMV_EL2 U(0x170)
+#define CTX_MPAM2_EL2 U(0x108)
+#define CTX_MPAMHCR_EL2 U(0x110)
+#define CTX_MPAMVPM0_EL2 U(0x118)
+#define CTX_MPAMVPM1_EL2 U(0x120)
+#define CTX_MPAMVPM2_EL2 U(0x128)
+#define CTX_MPAMVPM3_EL2 U(0x130)
+#define CTX_MPAMVPM4_EL2 U(0x138)
+#define CTX_MPAMVPM5_EL2 U(0x140)
+#define CTX_MPAMVPM6_EL2 U(0x148)
+#define CTX_MPAMVPM7_EL2 U(0x150)
+#define CTX_MPAMVPMV_EL2 U(0x158)
// Starting with Armv8.6
-#define CTX_HAFGRTR_EL2 U(0x178)
-#define CTX_HDFGRTR_EL2 U(0x180)
-#define CTX_HDFGWTR_EL2 U(0x188)
-#define CTX_HFGITR_EL2 U(0x190)
-#define CTX_HFGRTR_EL2 U(0x198)
-#define CTX_HFGWTR_EL2 U(0x1a0)
-#define CTX_CNTPOFF_EL2 U(0x1a8)
+#define CTX_HAFGRTR_EL2 U(0x160)
+#define CTX_HDFGRTR_EL2 U(0x168)
+#define CTX_HDFGWTR_EL2 U(0x170)
+#define CTX_HFGITR_EL2 U(0x178)
+#define CTX_HFGRTR_EL2 U(0x180)
+#define CTX_HFGWTR_EL2 U(0x188)
+#define CTX_CNTPOFF_EL2 U(0x190)
// Starting with Armv8.4
-#define CTX_CNTHPS_CTL_EL2 U(0x1b0)
-#define CTX_CNTHPS_CVAL_EL2 U(0x1b8)
-#define CTX_CNTHPS_TVAL_EL2 U(0x1c0)
-#define CTX_CNTHVS_CTL_EL2 U(0x1c8)
-#define CTX_CNTHVS_CVAL_EL2 U(0x1d0)
-#define CTX_CNTHVS_TVAL_EL2 U(0x1d8)
-#define CTX_CNTHV_CTL_EL2 U(0x1e0)
-#define CTX_CNTHV_CVAL_EL2 U(0x1e8)
-#define CTX_CNTHV_TVAL_EL2 U(0x1f0)
-#define CTX_CONTEXTIDR_EL2 U(0x1f8)
-#define CTX_SDER32_EL2 U(0x200)
-#define CTX_TTBR1_EL2 U(0x208)
-#define CTX_VDISR_EL2 U(0x210)
-#define CTX_VNCR_EL2 U(0x218)
-#define CTX_VSESR_EL2 U(0x220)
-#define CTX_VSTCR_EL2 U(0x228)
-#define CTX_VSTTBR_EL2 U(0x230)
-#define CTX_TRFCR_EL2 U(0x238)
+#define CTX_CONTEXTIDR_EL2 U(0x198)
+#define CTX_SDER32_EL2 U(0x1a0)
+#define CTX_TTBR1_EL2 U(0x1a8)
+#define CTX_VDISR_EL2 U(0x1b0)
+#define CTX_VNCR_EL2 U(0x1b8)
+#define CTX_VSESR_EL2 U(0x1c0)
+#define CTX_VSTCR_EL2 U(0x1c8)
+#define CTX_VSTTBR_EL2 U(0x1d0)
+#define CTX_TRFCR_EL2 U(0x1d8)
// Starting with Armv8.5
-#define CTX_SCXTNUM_EL2 U(0x240)
+#define CTX_SCXTNUM_EL2 U(0x1e0)
/* Align to the next 16 byte boundary */
-#define CTX_EL2_SYSREGS_END U(0x250)
+#define CTX_EL2_SYSREGS_END U(0x1f0)
#endif /* CTX_INCLUDE_EL2_REGS */