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authorAlexei Fedorov <Alexei.Fedorov@arm.com>2021-04-12 12:49:54 +0100
committerAlexei Fedorov <Alexei.Fedorov@arm.com>2021-04-21 14:38:15 +0200
commitdfa6c540713ba546da65fe179ec1ef0fc1b1f7f5 (patch)
tree2da4ef2c29e9767e078e5754b39918bf580b8d82 /include
parent617632bf834009b29eb1f659fbd971a139a899af (diff)
downloadtrusted-firmware-a-dfa6c540713ba546da65fe179ec1ef0fc1b1f7f5.tar.gz
Plat FVP: Fix Generic Timer interrupt types
The Arm Generic Timer specification mandates that the interrupt associated with each timer is low level triggered, see: Arm Cortex-A76 Core: "Each timer provides an active-LOW interrupt output to the SoC." Arm Cortex-A53 MPCore Processor: "It generates timer events as active-LOW interrupt outputs and event streams." The following files in fdts\ fvp-base-gicv3-psci-common.dtsi fvp-base-gicv3-psci-aarch32-common.dtsi fvp-base-gicv2-psci-aarch32.dts fvp-base-gicv2-psci.dts fvp-foundation-gicv2-psci.dts fvp-foundation-gicv3-psci.dts describe interrupt types as edge rising IRQ_TYPE_EDGE_RISING = 0x01: interrupts = <1 13 0xff01>, <1 14 0xff01>, <1 11 0xff01>, <1 10 0xff01>; , see include\dt-bindings\interrupt-controller\arm-gic.h: which causes Linux to generate the warnings below: arch_timer: WARNING: Invalid trigger for IRQ5, assuming level low arch_timer: WARNING: Please fix your firmware This patch adds GIC_CPU_MASK_RAW macro definition to include\dt-bindings\interrupt-controller\arm-gic.h, modifies interrupt type to IRQ_TYPE_LEVEL_LOW and makes use of type definitions in arm-gic.h. Change-Id: Iafa2552a9db85a0559c73353f854e2e0066ab2b9 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/interrupt-controller/arm-gic.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h
index aa9158cb1b..024a6c6026 100644
--- a/include/dt-bindings/interrupt-controller/arm-gic.h
+++ b/include/dt-bindings/interrupt-controller/arm-gic.h
@@ -18,4 +18,9 @@
#define IRQ_TYPE_LEVEL_HIGH 4
#define IRQ_TYPE_LEVEL_LOW 8
+/*
+ * Interrupt specifier cell 2.
+ */
+#define GIC_CPU_MASK_RAW(x) ((x) << 8)
+
#endif