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authorAntonio Niño Díaz <antonio.ninodiaz@arm.com>2019-02-22 15:23:52 +0000
committerGitHub <noreply@github.com>2019-02-22 15:23:52 +0000
commitab3d22473df279c61ed4d4873d26b072dcf887e8 (patch)
treebcfbba7909ca4be9bb71c2324be9fb43d65168ea /include
parent3f995f3078a9a22c5079e3d05995e26173ff6499 (diff)
parentb053a22e8a538d3ee6114c0ce7f25fa49f0302d8 (diff)
downloadtrusted-firmware-a-ab3d22473df279c61ed4d4873d26b072dcf887e8.tar.gz
Merge pull request #1836 from Yann-lms/docs_and_m4
Update documentation for STM32MP1 and add Cortex-M4 support
Diffstat (limited to 'include')
-rw-r--r--include/drivers/st/stm32mp1_clk.h1
-rw-r--r--include/drivers/st/stm32mp1_rcc.h4
2 files changed, 5 insertions, 0 deletions
diff --git a/include/drivers/st/stm32mp1_clk.h b/include/drivers/st/stm32mp1_clk.h
index 1e0d949ac5..7afa5ad845 100644
--- a/include/drivers/st/stm32mp1_clk.h
+++ b/include/drivers/st/stm32mp1_clk.h
@@ -13,6 +13,7 @@ int stm32mp1_clk_probe(void);
int stm32mp1_clk_init(void);
bool stm32mp1_rcc_is_secure(void);
+bool stm32mp1_rcc_is_mckprot(void);
void __stm32mp1_clk_enable(unsigned long id, bool caller_is_secure);
void __stm32mp1_clk_disable(unsigned long id, bool caller_is_secure);
diff --git a/include/drivers/st/stm32mp1_rcc.h b/include/drivers/st/stm32mp1_rcc.h
index 1922c48154..eaa853da34 100644
--- a/include/drivers/st/stm32mp1_rcc.h
+++ b/include/drivers/st/stm32mp1_rcc.h
@@ -111,6 +111,7 @@
#define RCC_RCK4SELR U(0x824)
#define RCC_TIMG1PRER U(0x828)
#define RCC_TIMG2PRER U(0x82C)
+#define RCC_MCUDIVR U(0x830)
#define RCC_APB1DIVR U(0x834)
#define RCC_APB2DIVR U(0x838)
#define RCC_APB3DIVR U(0x83C)
@@ -237,6 +238,7 @@
/* Values for RCC_TZCR register */
#define RCC_TZCR_TZEN BIT(0)
+#define RCC_TZCR_MCKPROT BIT(1)
/* Used for most of RCC_<x>SELR registers */
#define RCC_SELR_SRC_MASK GENMASK(2, 0)
@@ -273,6 +275,7 @@
#define RCC_APBXDIV_MASK GENMASK(2, 0)
#define RCC_MPUDIV_MASK GENMASK(2, 0)
#define RCC_AXIDIV_MASK GENMASK(2, 0)
+#define RCC_MCUDIV_MASK GENMASK(3, 0)
/* Used for TIMER Prescaler */
#define RCC_TIMGXPRER_TIMGXPRE BIT(0)
@@ -421,6 +424,7 @@
/* Global Reset Register */
#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
+#define RCC_MP_GRSTCSETR_MCURST BIT(1)
#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
#define RCC_MP_GRSTCSETR_MPUP1RST BIT(5)